.
IBMB6N32644JGA
Preliminary
Features
32Mx64 Two Bank Unbuffered DDR SDRAM Module
• DRAM D aligns DQ and DQS transitions with
LL
clock transitions. Also aligns QFC transitions
with clock during Read cycles
• Differential clock inputs
• Data is read or written on both clock edges
• Address and control signals are fully synchro-
nous to positive clock edge
• 184-Pin Unbuffered 8-Byte Dual In-Line
Memory Module
• 32Mx64 Double Data Rate (DDR) SDRAM
DIMM (16M X 8 SDRAMS)
• Performance:
• Programmable Operation:
PC1600 PC2100
Units
DIMM CAS Latency
Clock Frequency
Clock Cycle
2
2.5
133
7.5
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
f
t
f
100
10
MHz
ns
CK
CK
DQ
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 12/10/2 Addressing (row/column/bank)
• 15.6 µs Max. Average Periodic Refresh Interval
• Card size: 5.25" x 0.157" x 1.25"
• Gold contacts
DQ Burst Frequency
200
266
MHz
• Intended for 100 MHz and 133 MHz applica-
tions
• Inputs and outputs are SSTL-2 compatible
• V = 2.5Volt ± 0.2, V
= 2.5Volt ± 0.2
DD
DDQ
• Single Pulsed RAS interface
• SDRAMs have four internal banks for concur-
rent operation
• SDRAMS in 66-pin TSOP-II Package
• Serial Presence Detect
• Module has two physical banks
Description
IBMB6N32644JGA is an unbuffered 184-Pin Double
Data Rate (DDR) Synchronous DRAM Dual In-Line
Memory Module (DIMM), organized as a two-bank
high-speed memory array. The 32Mx64 module is a
dual-bank DIMM that uses sixteen 16Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM
achieves high-speed data transfer rates of up to 266
MHz.
be programmed into the DIMM by address inputs
A0-A11 and I/O inputs BA0 and BA1 using the
mode register set cycle.
These DIMMs are manufactured using raw cards
developed for broad industry use as reference
designs. The use of these common design files min-
imizes electrical variation between suppliers.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
programmed and locked during module assembly.
The last 128 bytes are available to the customer.
The DIMM is intended for use in applications oper-
ating from 100 MHz to 133 MHz clock speeds with
data rates of 200 to 266 MHz.
Clock enables CKE0 and/or CKE1 control all
devices on the DIMM.
All IBM 184 DDR SDRAM DIMMs provide a high-
performance, flexible 8-byte interface in a 5.25” long
space-saving footprint.
Prior to any access operation, the device CAS
latency and burst type/length/operation type must
Card Outline
1
92
184
(Front)
(Back) 93
52 53
144 145
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
88H4717.H41859
12/00
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