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IBMB6M32734HGA
Preliminary
Features
32Mx72 One Bank Registered DDR SDRAM Module
preamble and one-half clock post-amble
• Differential clock inputs
• Data is read or written on both clock edges
• Address and control signals are fully synchro-
nous to positive clock edge
• 184-Pin Registered 8-Byte Dual In-Line Memory
Module
• 32Mx72 Double Data Rate (DDR) SDRAM
DIMM (32M X 8 SDRAMS)
• Programmable Operation:
• Performance:
- DIMM CAS Latency: 3, 3.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
PC1600
Units
DIMM CAS Latency
Clock Frequency
Clock Cycle
3
3.5
125
8.0
f
t
f
100
10
MHz
ns
CK
CK
DQ
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• Power Down Mode
DQ Burst Frequency
200
250
MHz
• Intended for 100 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V = 2.5Volt ± 0.2, V = 2.5Volt ± 0.2
• 13/10/2 Addressing (row/column/bank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Card size: 5.25" x 0.157" x 1.70"
• Gold contacts
• SDRAMS in 66-pin TSOP-II Package
• Serial Presence Detect
DD
DDQ
• Single Pulsed RAS interface
• SDRAMs have four internal banks for concur-
rent operation
• Module has one physical bank
• Bi-directional data strobe with one clock cycle
Description
IBMB6M32734HGA is a registered 184-Pin Double
Data Rate (DDR) Synchronous DRAM Dual In-Line
Memory Module (DIMM), organized as a one-bank
high-speed memory array. The 32Mx72 module is a
single-bank DIMM that uses nine 32Mx8 DDR
SDRAMs in 400 mil TSOP packages. This DIMM
achieves high-speed data transfer rates of up to 250
MHz.
be programmed into the DIMM by address inputs
A0-A12 and I/O inputs BA0 and BA1 using the
mode register set cycle. The DIMM CAS latency
exceeds the SDRAM device specification by one
clock due to the address and control signals being
clocked to the SDRAM devices.
These DIMMs are manufactured using raw cards
developed for broad industry use by IBM as refer-
ence designs. The use of these common design
files will minimize electrical variation between sup-
pliers.
The DIMM is intended for use in applications oper-
ating from 100 MHz to 125 MHz clock speeds with
data rates of 200 to 250 MHz. All control and
address signals are re-driven through registers to
the DDR SDRAM devices. The control and address
input signals are latched in the register on one rising
clock edge and sent to the SDRAM devices on the
following rising clock edge.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
programmed and locked during module assembly.
The last 128 bytes are available to the customer.
A phase-locked loop (PLL) on the DIMM is used to
re-drive the differential clock signals to both the
DDR SDRAM devices and the registers, thus mini-
mizing system clock loading. Clock enable (CKE0)
controls all devices on the DIMM.
All IBM 184 DDR SDRAM DIMMs provide a high-
performance, flexible 8-byte interface in a 5.25” long
space-saving footprint.
Prior to any access operation, the device CAS
latency and burst type/length/operation type must
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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