IBM PowerPRS C192
Summary Datasheet
Preliminary
Common Switch Interface
General Information
Features
• Companion to the IBM PowerPRS 64G and
• Configurable number of traffic priorities (from
two to four)
PowerPRS Q-64G Packet Routing Switch chips
• Direct attachment to the IBM PowerPRS Switch
Core Interface Chip (SCIC), the Unilink to
PowerPRS 64G-compatible data-aligned syn-
chronous link (DASL) converter
• Packet header parity generation and checking
• End-to-end packet payload protection, with
optional cyclic redundancy check (CRC)
insertion
• CSIX interface attachment to PowerPRS 64G
and PowerPRS Q-64G switch cores
• Programmable generation and detection of link
liveness messages in yellow packets
• CSIX-L1 interface: OC-48 and OC-192 adapter,
compliant with the Common Switch Interface -
Level 1 specification
• Eight-bit parallel processor interface to access
all registers for control and error reporting
• Internal loopback support for both the switch
interface and CSIX adapter interface
• Redundant switch port attachment at 16 Gbps
using 2.5-Gbps serial links compatible with
InfiniBand physical layer standards
• Internal logic built-in self-test (BIST) and
memory BIST
• Dual-switch attachment for redundant switch-
plane operation, including programmable
scheduled switchover (packet lossless) and
hot standby switchover
• SA-27E technology (Ldrawn = 0.18 µm,
Leff = 0.11 µm):
- 1.8-V core voltage
• PowerPRS 64G interface: 16- to 20-byte logical
unit (LU) packet processing with four-way port
paralleling
- 2.5-V LVCMOS-compatible (3.3-V tolerant)
I/Os for microprocessor interface
- 2.5-V LVCMOS- or 1.5-V HSTL-compatible
I/Os for CSIX-L1 interface
• PowerPRS Q-64G interface: 8- to 10-byte LU
packet processing with two-way port paralleling
• IEEE Standard 1149.1 boundary scan to facili-
tate circuit-board testing
• Shared buffer capacity of up to 2048 ingress
packets (1024 per switch plane) and up to 1024
egress packets (shared between switch planes)
• 840-ball IBM HyperBGA package
Description
The IBM PowerPRS C192 Common Switch Inter-
face is a companion device to the IBM PowerPRS
64G and PowerPRS Q-64G Packet Routing
Switches. It functions as the switch core access
layer between the protocol engine’s four OC-48 or
OC-192 CSIX interfaces and the switch core. The
PowerPRS C192 switch interface is comprised of
eight 2.5-Gbps Unilink pairs that provide a total
throughput of 20 Gbps. The switch port payload
throughput is 16 Gbps because the Unilinks use
the same 8b/10b line coding scheme as the fiber
channel standard.
In PowerPRS 64G applications, the PowerPRS
C192 is attached to the PowerPRS SCIC, which
converts the 8 Unilinks into 32 PowerPRS 64G-
compatible data-aligned synchronous links (DASLs).
The packet length in the PowerPRS 64G, SCIC,
and C192 is programmable from 64 to 80 bytes, in
4-byte increments. Packets flowing to (ingress) and
from (egress) the PowerPRS 64G are divided into
four logical units (LUs) of 16 to 20 bytes each,
depending on the packet length. In PowerPRS 64G
applications, the PowerPRS C192 processes four
packets in parallel.
C192sds.00.fm
September 7, 2001
General Information
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