Preliminary
PowerPC 440GX Embedded Processor Data Sheet
Features
®
• TCP/IP Acceleration Hardware (TAH) provided
for 10/100/1000 Mbps ports that performs
checksum processing, TCP segmentation, and
includes support for jumbo frames
• PowerPC 440 processor core operating up to
800MHz with 32KB I- and D-caches (with parity
checking)
• On-chip 256KB SRAM configurable as L2 Code
store or Ethernet Packet store memory
• Two Ethernet 10/100Mbps half- or full-duplex
interfaces. Operational modes supported are
MII, RMII, and SMII.
• Selectable processor:bus clock ratios (Refer to
the Clocking chapter in the PPC440GX
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
Embedded Processor User’s Manual for details)
• Double Data Rate (DDR) Synchronous DRAM
(SDRAM) interface operating up to 166MHz
• I2O Messaging unit for message transfer
between the CPU and PCI-X
• External Peripheral Bus (32 bits) for up to eight
devices with external mastering
• Programmable General Purpose Timers (GPT)
• Two serial ports (16750 compatible UART)
• Two IIC interfaces
• DMA support for external peripherals, internal
UART and memory
• PCI-X V1.0a interface (32 or 64 bits, up to
133MHz) with support for conventional PCI
V2.3
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• Processor can boot from PCI memory
• Available in ceramic and plastic packages
• Two Ethernet 10/100/1000Mbps half- or full-
duplex interfaces. Operational modes
supported are SMII, GMII, RGMII, TBI and
RTBI.
Description
Designed specifically to address high-end
Technology: IBM CMOS Cu-11, 0.13µm , 6-layer
metal
embedded applications, the PowerPC 440GX
(PPC440GX) provides a high-performance, low
power solution that interfaces to a wide range of
peripherals by incorporating on-chip power
management features and lower power dissipation.
Packages: 25mm, 552-ball Ceramic Ball Grid Array
(CBGA) or Plastic Ball Grid Array (PBGA)
Power (estimated): Less than:
4W typical @533MHz
This chip contains a high-performance RISC
processor core, DDR SDRAM controller,
configurable 256KB SRAM to be used as L2 cache
or software-controlled on-chip memory, PCI-X bus
interface, Gigabit Ethernet interfaces, TCP/IP
acceleration hardware, I2O messaging unit, control
for external ROM and peripherals, DMA with
scatter-gather support, serial ports, IIC interface,
and general purpose I/O.
5W typical @667MHz
6W typical @800MHz (estimated)
Supply voltages required: 3.3V, 2.5V, 1.5V
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
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6/30/04
IBM [ IBM ]
