PowerPC 405GP Embedded Processor Data Sheet
Features
TM
- Internal PCI Bus Arbiter which can be
• IBM PowerPC 405 32-bit RISC processor
core operating up to 266 MHz
disabled for use with an external arbiter
• Ethernet 10/100Mbps (full-duplex) support with
Medium Independent Interface (MII)
• PC-100 Synchronous DRAM (SDRAM)
interface operating up to 133 MHz
• Programmable Interrupt Controller supports
interrupts from a variety of sources
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
- Seven external and 19 internal
- Edge triggered or level-sensitive
- Positive or negative active
• 4KB On-chip Memory (OCM)
• External Peripheral Bus
- Non-critical or critical interrupt to processor
core
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM
and external peripherals
- Programmable critical interrupt priority
ordering
- Up to eight devices
- Programmable critical interrupt vector for
faster vector processing
- External Mastering supported
• DMA support for external peripherals, internal
UART and memory
• Programmable Timers
• Two serial ports (16550 compatible UART)
- Scatter-gather chaining supported
- Four channels
2
• One IIC (I C) interface
• General Purpose I/O (GPIO) available
• Supports JTAG for board level testing
• PCI Revision 2.2 Compliant Interface (32-bit, up
to 66MHz)
- PCI Bus interface can be configured to
operate synchronously or asynchronously
to the chip input clock
• Internal Processor Local Bus (PLB) runs at
SDRAM interface frequency
• Supports PowerPC processor boot from PCI
memory
Description
Designed specifically to address embedded
applications, the PowerPC 405GP (PPC405GP)
provides a high-performance, low-power solution
that interfaces to a wide range of peripherals by
incorporating on-chip power management features
and intrinsically lower power dissipation
requirements.
ROM and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general
purpose I/O.
Technology: IBM CMOS SA12E 0.25 µm
(0.18 µm L )
eff
Package: 456-ball (35mm or 27mm), or 413-ball
(25mm) enhanced plastic ball grid array (E-PBGA)
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus
interface, Ethernet interface, control for external
Power (estimated): Typical 1.5W, Maximum 2.0W
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made
1
IBM [ IBM ]
