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IBM25NPE405L-3FA133CZ 参数 Datasheet PDF下载

IBM25NPE405L-3FA133CZ图片预览
型号: IBM25NPE405L-3FA133CZ
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 133MHz, CMOS, PBGA324, 23 X 23 MM, PLASTIC, EBGA-324]
分类和应用: 时钟外围集成电路
文件页数/大小: 52 页 / 907 K
品牌: IBM [ IBM ]
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Preliminary  
PowerNP NPe405L Embedded Processor Data Sheet  
Features  
• PowerNPtechnology using an IBM PowerPC  
405 32-bit RISC processor core operating up to  
266 MHz  
• HDLC interface with 32 channels through two  
ports at up to 4.096 Mbps each or 8.192 Mbps  
for a single port  
• Programmable interrupt controller  
- Seven external and 29 internal  
- Edge triggered or level-sensitive  
- Positive or negative active  
• PC-133 synchronous DRAM (SDRAM) interface  
- 32-bit interface for non-ECC applications  
- 40-bit interface serves 32 bits of data plus 8  
check bits for ECC applications  
• External bus for peripheral devices  
- Flash and ROM interface  
- Non-critical or critical interrupt to processor  
core  
- Programmable critical interrupt priority  
ordering  
- Direct support for 8-, or 16-bit SRAM and  
external peripherals  
- Programmable critical interrupt vector  
• Programmable timers  
- Up to 4 devices  
• DMA support for external peripherals, internal  
UARTs and memory  
• Two serial ports (16550 compatible UART)  
• One IIC interface  
- Scatter-gather chaining supported  
- Four channels  
• General Purpose I/O (GPIO) available  
• Supports JTAG for board level testing  
• Two 10/100 Ethernet MACs supporting up to  
two external PHYs via MII, RMII, or SMII  
interfaces  
• Internal processor local bus (PLB) runs at  
SDRAM interface frequency  
Description  
Designed specifically to address embedded  
applications, the NPe405L provides a high-  
performance, low-power solution that interfaces to a  
wide range of peripherals by incorporating on-chip  
power management features and lower power  
dissipation requirements.  
ROM, Flash, and peripherals, DMA with scatter-  
gather support, serial ports, IIC interface, and  
general purpose I/O.  
Technology: IBM CMOS SA-12E 0.25 µm  
(0.18 µm Leff)  
Package: 23mm, 324-ball enhanced plastic ball grid  
array (E-PBGA)  
Power (typical): 1.3W at 133MHz, 1.7W at  
200MHz, 1.8W at 266MHz  
This chip contains a high-performance RISC  
processor core, SDRAM controller, Ethernet  
EMACs, HDLC controller, external bus controller for  
While the information contained herein is believed to be accurate, such information is preliminary, and should not be  
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.  
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