Preliminary
PowerNP NPe405H Embedded Processor Data Sheet
Features
• PowerNP technology using an IBM PowerPC
405 32-bit RISC processor core operating up to
266 MHz
• HDLC interface with 32 channels through two
ports at up to 4.096 Mbps each or 8.192 Mbps
for a single port
• HDLC interface with 8 channels through 8 ports
at 2.048 Mbps maximum
• PC-133 synchronous DRAM (SDRAM) interface
- 32-bit interface for non-ECC applications
• Programmable interrupt controller
- Seven external and 49 internal
- Edge triggered or level-sensitive
- Positive or negative active
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
• External bus for peripheral devices
- Flash and ROM interface
- Non-critical or critical interrupt to processor
core
- Direct support for 8-, or 16-, or 32-bit SRAM
and external peripherals
- Programmable critical interrupt priority
ordering
- Up to 8 devices
- External mastering supported
- Programmable critical interrupt vector
• Programmable timers
• DMA support for external peripherals, internal
UARTs and memory
• Two serial ports (16550 compatible UART)
• One IIC interface
- Scatter-gather chaining supported
- Four channels
• PCI Revision 2.2 compliant interface (32-bit, up
to 66MHz)
• General Purpose I/O (GPIO) available
• Supports JTAG for board level testing
- Asynchronous PCI bus interface
• Internal processor local bus (PLB) runs at
SDRAM interface frequency
- Internal PCI bus arbiter which can be
disabled for use with an external arbiter
• Supports PowerPC processor boot from PCI
memory
• Four 10/100 Ethernet MACs supporting up to
four external PHYs via MII, RMII, or SMII
interfaces
• User accessible performance counters
Description
Designed specifically to address embedded
applications, the NPe405H provides a high-
performance, low-power solution that interfaces to a
wide range of peripherals by incorporating on-chip
power management features and lower power
dissipation requirements.
controller for ROM, Flash, and peripherals, DMA
with scatter-gather support, serial ports, IIC
interface, and general purpose I/O.
Technology: IBM CMOS SA-12E 0.25 µm
(0.18 µm Leff)
Package: 35mm, 580-ball enhanced plastic ball grid
array (E-PBGA)
Power (typical): 2.3W at 133MHz, 2.9W at
200MHz, 3.4W at 266MHz
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus bridge,
Ethernet EMACs, HDLC controllers, external bus
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
1
IBM [ IBM ]
