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IBM21S761 参数 Datasheet PDF下载

IBM21S761图片预览
型号: IBM21S761
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, PQFP80, 12 X 12 MM, LQFP-80]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 43 页 / 536 K
品牌: IBM [ IBM ]
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IBM21S760  
IBM21S761  
IBM 1394 200Mb/s Physical Layer Transceiver (PHY)  
Features  
• Designed to provisions of the IEEE 1394 Serial  
Bus Standard [1]  
• 200Mb/s max data rate; interoperable with  
100Mb/s devices  
• Available with one or three ports  
• Supports major P1394a enhancements  
- Multi-speed Concatenation  
- Arbitrated Short Reset  
• Advanced Power Management:  
- Programmable Power Save Mode on uncon-  
nected ports  
- Sleep Mode to minimize quiescent power  
- Utilizes sophisticated clock gating to reduce  
power consumption  
Tolerant of extra IDLE indications which circum-  
vents Link-PHY “Bus Collision” conditions  
• On-device PLL generates the 50MHz SCLK  
using an external 25MHz crystal oscillator  
• Supports optional 1394-1995 Isolation Barrier  
Feature at Link-PHY Interface  
- ACK Accelerated Arbitration  
- Three TpBias Regulators  
- Connection Debounce  
• “Missing SID bits” register  
• “No reset on unplug” option  
• Fully Compliant with OpenHCI requirements  
- Programmable Port Disable  
- No phy_ID wrap past 63  
• Supports optional IBM Dynamic Termination  
Isolation Barrier Feature at Link-PHY Interface  
• Interoperable with 5V Link Layer Controllers and  
5V Transceivers  
• Selectable Link-PHY interface timings  
• Single 3.3V power supply  
• Cable ports exceed 5kV of ESD protection  
(Human Body Model)  
Overview  
The IBM21S760 and IBM21S761 devices (PHYs)  
provide transceivers to implement a three or one  
port node in a 1394 cable based network. The PHY  
is designed to the provisions of the IEEE 1394-1995  
specification [1] and includes many of the P1394a  
[2] and all OpenHCI enhancements. These  
enhancements include Arbitrated Short Reset (for  
uninterrupted Isochronous data transport), multi-  
speed concatenation, ACK Accelerated Arbitration  
(to improve bandwidth utilization), Connection  
Debounce Hysteresis (to avoid “Reset Storms”),  
three independent TpBias regulators (providing the  
ability to disable individual ports), and numerous  
other features.  
PHY at the other end of the cable.  
In addition to providing bus transceivers, the PHY  
serializes and deserializes data using Data and  
Strobe encoding. Data is sent from the Link Layer  
Controller on an eight bit wide parallel bus to the  
PHY. The two devices are synchronized by a  
49.152MHz reference clock provided by the PHY.  
The data is then serialized and transmitted to the  
cable as Strobe on TPA and Data on TPB. Received  
data is resynchronized to the reference clock and  
decoded for parallel transmission to the Link Layer  
Controller.  
PHY devices communicate their speed capabilities  
to one another through a process called Speed Sig-  
naling, in which common mode currents are with-  
drawn from the cable at TPB and TPB. Two such  
common mode currents exist for this PHY: one for  
each of the supported transfer speeds. The nominal  
common mode currents are defined for 100Mb/s and  
200Mb/s as 0mA and -3.5mA respectively. The PHY  
is capable of 100 or 200Mb/s operation, and will  
send or receive data at any of these speeds accord-  
ing to the capabilities of the adjacent PHYs.  
Each cable port is composed of two differential line  
transceivers (TPA and TPB) that transmit and  
receive serial data at 100 or 200Mb/s (actually  
98.304 or 196.608Mb/s respectively), depending on  
which data speed is routed through the bus. Each  
transceiver contains a differential current mode  
driver whose outputs provide signal swings around a  
common mode voltage called TpBias, which is gen-  
erated on the PHY device. Two off-device 55 ohm  
resistors are connected in series across the differen-  
tial outputs of each transceiver. TpBias voltage is  
connected to the midpoint connection of the resis-  
tors at TPA, while a 5K ohm resistor and a 250pF  
capacitor to ground are attached to the midpoint  
connection of the resistors at TPB. The TpBias volt-  
age for the TPB line is supplied by the TPA of the  
Other functions of the PHY include system initializa-  
tion and bus arbitration. The PHY also determines  
whether its ports are connected to other ports by  
detecting the presence or absence of TpBias volt-  
age from the other transceiver. Moreover, it func-  
©IBM Corporation 1997, 1998. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
phy200.02  
11/24/98  
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