IBM21S650PFA
1394 Serial Bus Link Layer PCI Controller
Features
• Fully IEEE 1394-1995 compatible
• General purpose IEEE 1394 Host Controller
• Asynchronous and isochronous capability
• Data rates: S100, S200, or S400Mb/s
• Uses DB DMA channel programs to communi-
cate with the device driver.
• Cycle Master capable
• ROM interface for external configuration ROM
• PCI 2.1 compatible, with master and slave capa-
bilities
• Standard Link-PHY protocol and an Isolation
barrier between the link controller and the PHY
as described in IEEE 1394 Specification,
Annex J
• 33MHz PCI bus support
• Parity error detection and report
• CMOS5S technology
• Transmits and receives packets larger than the
2KB internal buffer size.
• 3.3V power supply with 5.0V tolerant I/O
• 144 pin LQFP package
• Supports data chaining for packets and indi-
cates status of each package
Description
The IBM21S650PFA is a generic Link Layer Control-
ler for the 1394 serial bus using a PCI system inter-
face. It supports the transaction and bus
PCI to 1394 Interface System Example
management layers with an additional PHY device
and includes a DMA engine to reduce the CPU inter-
vention in transmitted or received packets.
CPU
Host Bridge
DRAM
PCI Bus
This link controller transmits and receives all types
of asynchronous packets, including cable physical
layer packets. It supports four isochronous DMA
channels, each of which can be programmed for
transmit or receive operation.
• Supports Packet-by-Packet and Contiguous
modes in receive.
• Supports Scatter & Gather of data in transmit
and receive operations.
Link Controller
PCI Component
PHY
1394 Bus
1394
1394
device
1394
device
1394
device
1394
device
• Supports starting/stopping the channel opera-
tion.
device
• Supports cycle count information per packet for
receive.
The IBM21S650PFA has additional features. It can
function as PCI master, supporting cache line com-
mands, or as a PCI slave, supporting memory or
configuration access as a medium speed target.
During a 1394 bus reset, it receives the Self ID
packets from the PHY and forwards them to the sys-
tem memory. The link controller also has an external
port that allows direct access from the host CPU to
an expansion ROM or configuration ROM.
©IBM Corporation 1997, 1998. All rights reserved.
Use is further subject to the provisions at the end of this document.
21S650pfa.00
12/18/98
Page 1 of 86
IBM [ IBM ]
