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IBM13N64644HCA
IBM13N64734HCA
Preliminary
Features
64M x 64/72 Two-Bank Unbuffered SDRAM Module
• 168-Pin Unbuffered 8-Byte Dual In-Line Memory
• Automatic and controlled Precharge commands
• Programmable Operation:
Module
• 64Mx64/72 Synchronous DRAM DIMM
• Intended for PC133 applications
- CAS Latency: 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page (Full-
Page supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
• Clock Frequency: 133MHz
• Clock Cycle: 7.5ns
• Clock Assess Time: 5.4ns
• Suspend Mode and Power Down Mode
• 13/10/2 Addressing (Row/Column/Bank)
• 8192 Refresh cycles distributed across 64ms
• Serial Presence Detect with Write Protect
• Card size: 5.25" x 1.375" x 0.158" max
• Gold contacts
• Inputs and outputs are LVTTL (3.3V) compatible
• Single 3.3V ± 0.3V Power Supply
• Single Pulsed RAS interface
• SDRAMs have 4 internal banks
• Module has 2 Physical banks
• Fully Synchronous to positive Clock Edge
• Data Mask for Byte Read/Write control
• Auto Refresh (CBR) and Self Refresh
• DRAMs in TSOP Type II Package
Description
IBM13N64644HCA / IBM13N64734HCA are unbuf-
fered 168-pin Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as
64Mx64 and 64Mx72 high-speed memory arrays
and are configured as two 32M x 64/72 physical
banks. The DIMMs use sixteen (64Mx64) or eigh-
teen(64Mx72) 32Mx8 SDRAMs in 400mil TSOP II
packages. The DIMMs achieve high-speed data-
transfer rates of up to 133MHz by employing a
prefetch/pipeline hybrid architecture that supports
the JEDEC 1N rule while allowing very low burst
power.
A command decoder initiates the necessary timings
for each operation. A 15-bit address bus accepts
address information in a row/column multiplexing
arrangement.
Prior to any Access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the DIMM by address
inputs A0-A9 during the Mode Register Set cycle.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two pin IIC
protocol. The first 128 bytes of serial PD data are
used by the DIMM manufacturer. The last 128 bytes
are available to the customer.
All control, address, and data input/output circuits
are synchronized with the positive edge of the exter-
nally supplied clock inputs.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products include both EDO DRAM
and SDRAM unbuffered DIMMs in both non-parity
x64 and ECC-Optimized x72 configurations.
All inputs are sampled at the positive edge of each
externally supplied clock (CK0 - CK3). Internal oper-
ating modes are defined by combinations of RAS,
CAS, WE, S0-S3, DQMB, and CKE0-CKE1 signals.
Card Outline
(Front)
(Back)
10 11
94 95
84
1
40 41
124 125
168
85
09K3608.F38386
7/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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