.
IBM13N16644JCA
IBM13N16734JCA
16M x 64/72 One-Bank Unbuffered SDRAM Module
Features
• 168-Pin Unbuffered 8-Byte Dual In-Line Memory
Module
• Programmable Operation:
- CAS Latency: 3
• Intended for PC133 applications
• Clock Frequency: 133MHz
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page
(Full-Page supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
• Clock Cycle: 7.5ns
• Clock Assess Time: 5.4ns
• Inputs and outputs are LVTTL (3.3V) compatible
• Single 3.3V ± 0.3V Power Supply
• Single Pulsed RAS interface
• SDRAMs have 4 internal banks
• Module has 1 physical bank
• Fully Synchronous to positive Clock Edge
• Data Mask for Byte Read/Write control
• Auto Refresh (CBR) and Self Refresh
• Automatic and controlled Precharge commands
• Suspend Mode and Power Down Mode
• 12/10/2 Addressing (Row/Column/Bank)
• 4096 Refresh cycles distributed across 64ms
• Card size: 5.25" x 1.375" x 0.106"
• Gold contacts
• SDRAMs in TSOP Type II Package
• Serial Presence Detect with Write Protect
Description
IBM13N16644JCA / IBM13N16734JCA are unbuf-
fered 168-pin Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as
16Mx64 and 16Mx72 high-speed memory arrays
and are configured as one 16M x 64/72 physical
bank. The DIMMs use eight (16Mx64) or nine
(16Mx72) 16Mx8 SDRAMs in 400mil TSOP II pack-
ages. The DIMMs achieve high-speed data transfer
rates of up to 133MHz by employing a prefetch/pipe-
line hybrid architecture that supports the JEDEC 1N
rule while allowing very low burst power.
for each operation. A 14-bit address bus accepts
address information in a row/column multiplexing
arrangement.
Prior to any Access operation, the CAS latency,
burst type, burst length, and Burst operation type
must be programmed into the DIMM by address
inputs A0-A9 during the Mode Register Set cycle.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
used by the DIMM manufacturer. The last 128 bytes
are available to the customer.
All control, address, and data input/output circuits
are synchronized with the positive edge of the exter-
nally supplied clock inputs.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint. Related products include both EDO DRAM
and SDRAM unbuffered DIMMs in both non-parity
x64 and ECC-Optimized x72 configurations.
All inputs are sampled at the positive edge of each
externally supplied clock (CK0, CK2). Internal oper-
ating modes are defined by combinations of RAS,
CAS, WE, S0/S2, DQMB, and CKE0 signals. A
command decoder initiates the necessary timings
Card Outline
(Front)
(Back)
10 11
94 95
84
168
1
85
40 41
124 125
09K3606.F38386
8/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 18
IBM [ IBM ]
