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IBM11S4325HM-70T 参数 Datasheet PDF下载

IBM11S4325HM-70T图片预览
型号: IBM11S4325HM-70T
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM Module, 4MX32, 70ns, CMOS]
分类和应用: 动态存储器内存集成电路
文件页数/大小: 22 页 / 209 K
品牌: IBM [ IBM ]
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IBM11S2320NL2M  
x 3212/8, 5.0V, Au. IBM11S2320NN2M x 3212/8, 3.3V, Au.  
IBM11S2325HP IBM11S4325HP  
IBM11S2325HM IBM11S4325HM  
2M/4M x 32 SO DIMM Module  
Features  
• 72-Pin Small Outline Dual-In-Line  
Memory Module  
• Performance:  
• High Performance CMOS process  
• Single 3.3 ± 0.3V or 5.0 ± 0.25V Power Supply  
• Low active current consumption  
• All inputs & outputs are LVTTL(3.3V) or TTL(5V)  
compatible  
• Extended Data Out (EDO) access cycle  
• Refresh Modes: RAS-Only, CBR, Hidden and  
Self Refresh  
• 2048 refresh cycles distributed across 128ms  
• 11/10 Addressing (Row/Column)  
• Optimized for use in byte-write non-parity appli-  
cations.  
-60  
-6R  
-70  
tRAC  
tCAC  
tAA  
RAS Access Time  
CAS Access Time  
60ns 60ns 70ns  
15ns 17ns 20ns  
Access Time From Address 30ns 30ns 35ns  
tRC  
Cycle Time  
104ns 104ns 124ns  
25ns 25ns 30ns  
tHPC  
EDO Mode Cycle Time  
• Au contacts  
Description  
The IBM11S4325HP/M are 16MB industry standard  
72-pin 4-byte small outline dual in-line memory mod-  
ules (SO DIMMs). The modules are organized as  
4Mx32 high speed memory arrays that are intended  
for use in 16, 32 and 64 bit applications. They are  
manufactured with eight 2Mx8 TSOP devices, each  
in a 400mil package. The IBM11S1325HP/M are  
8MB half populated versions, manufactured with  
four 2Mx8 TSOP devices.  
60/6Rns sort). The use of TSOP packages allows  
for tight DIMM spacing (.3” on center). Input loading  
is consistent with 4Mb-based assemblies due to the  
addition of discrete capacitors maximizing compati-  
bility at the system level.  
These assemblies are intended for use in space  
constrained and/or low power applications.  
The IBM 72-Pin SO DIMMs provide a high perfor-  
mance, flexible 4-byte interface in a 2.35” long foot-  
print.  
The use of EDO DRAMs allows for a reduction in  
cycle time from 40ns (Fast Page) to 25ns (EDO,  
Card Outline  
Detail A  
See Detail A  
for 5.0V version  
(Front) 1  
(Back) 2  
71  
72  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
75H1718  
SA14-4471-00  
Revised 4/96  
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