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IBM11S1325LP-60T 参数 Datasheet PDF下载

IBM11S1325LP-60T图片预览
型号: IBM11S1325LP-60T
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM Module, 1MX32, 60ns, CMOS]
分类和应用: 动态存储器内存集成电路
文件页数/大小: 22 页 / 603 K
品牌: IBM [ IBM ]
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Discontinued (9/98 - last order; 3/99 last ship)  
IBM11S2320NL2M  
x 3212/8, 5.0V, Au. IBM11S2320NN2M x 3212/8, 3.3V, Au.  
IBM11S1325LP IBM11S2325LP  
1M/2M x 32 SO DIMM Module  
Features  
• 72-Pin Small Outline Dual-In-Line  
Memory Module  
• Performance:  
• High Performance CMOS process  
• Single 3.3 ± 0.3V Power Supply  
• Low active current consumption  
• All inputs & outputs are LVTTL(3.3V) compatible  
• Extended Data Out (EDO) access cycle  
• Refresh Modes: RAS-Only, CBR, Hidden and  
Self Refresh  
• 1024 refresh cycles distributed across 128ms  
• 10/10 Addressing (Row/Column)  
• Optimized for use in byte-write non-parity appli-  
cations.  
-60  
60ns  
15ns  
30ns  
104ns  
25ns  
tRAC  
tCAC  
tAA  
RAS Access Time  
CAS Access Time  
Access Time From Address  
Cycle Time  
tRC  
tHPC  
EDO Mode Cycle Time  
• Au contacts  
Description  
The IBM11S2325LP is an 8MB industry standard  
72-pin 4-byte small outline dual in-line memory  
module (SO DIMM). The module is organized as a  
2Mx32 dual bank high speed memory array that is  
intended for use in 16, 32 and 64 bit applications. It  
is manufactured with four 1Mx16 TSOP devices,  
each in a 400mil package.  
cycle time from 40ns (Fast Page) to 25ns (EDO,  
60ns sort). The use of TSOP packages allows for  
tight DIMM spacing (.3” on center). Input loading is  
consistent with 4Mb device-based assemblies due  
to the addition of discrete capacitors maximizing  
compatibility at the system level.  
These assemblies are intended for use in space  
constrained and or low power applications.  
The IBM11S1325LP is a 4MB half populated ver-  
sion, manufactured with two 1Mx16 TSOP devices  
and is organized as a single bank 1Mx32 high  
speed memory array.  
The IBM 72-Pin SO DIMMs provide a high perfor-  
mance, flexible 4-byte interface in a 2.35” long foot-  
print.  
The use of EDO DRAMs allows for a reduction in  
Card Outline  
(Front) 1  
(Back) 2  
71  
72  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
75H1720  
SA14-4472-01  
Revised 6/97