Discontinued (9/98 - last order; 3/99 last ship)
IBM11M4730C4M
x 72 E12/10, 5.0V, Au.
IBM11N8645H
IBM11N8735H
8M x 64/72 DRAM Module
Features
• 168 Pin JEDEC Standard, Unbuffered 8 Byte
Dual In-line Memory Module
• Optimized for byte-write non-parity, or ECC
applications
• 8Mx64, 8Mx72 Extended Data Out Mode
DIMMS
• System Performance Benefits:
- Non buffered for increased performance
- Reduced noise (35 V /V pins)
- Byte write, byte read accesses
- Serial PDs
SS CC
• Performance:
-50
-60
RAS Access Time
CAS Access Time
Access Time From Address
Cycle Time
50ns
13ns
25ns
60ns
15ns
30ns
tRAC
tCAC
• Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
tAA
• Refresh Modes: RAS-Only, CBR and Hidden
Refresh
84ns 104ns
20ns 25ns
tRC
tHPC
EDO Mode Cycle Time
• 4096 refresh cycles distributed across 64ms
• 12/11 addressing (Row/Column)
• Card size: 5.25" x 1.0" x 0.157"
• DRAMS in TSOP Package
• Inputs and outputs are LVTTL (3.3V) compatible
• Single 3.3V ± 0.3V Power Supply
• Gold contacts
Description
IBM11N8645H/IBM11N8735H are industry standard
168-pin 8-byte Dual In-line Memory Modules
(DIMMs) which are organized as 8Mx64 and 8Mx72
high speed memory arrays designed with EDO
DRAMs for non-parity or ECC applications. The
DIMMs use 8 (x64) or 9 (x72) 8Mx8 EDO DRAMs in
TSOP packages. The use of EDO DRAMs allows for
a reduction in Page Mode Cycle time from 40ns
(Fast Page) to 20ns for 50ns DRAM modules.
clock data between the master (system logic) and
the slave EEPROM device (DIMM). The EEPROM
device address pins (SA0-2) are brought out to the
DIMM tabs to allow 8 unique DIMM/EEPROM
addresses. The first 128 bytes are utilized by the
DIMM manufacturer and the second 128 bytes of
serial PD data are available to the customer.
All IBM 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint. Related products include the buffered
DIMMs (x64 non- parity and x72 ECC Optmized) for
applications which can benefit from the on-card buff-
ers.
The DIMMs use serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. This communication protocol uses Clock
(SCL) and Data I/O (SDA) lines to synchronously
Card Outline
(Front)
(Back)
1
85
10 11
94 95
84
168
40 41
124 125
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
54H8530.E24352A
Revised 4/98
Page 1 of 31
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