IBM11M8735CB8M
x 72 E12/10, 3.3V, Au, EDOMMDL11DSU-011021129. IBM11M8735C8M x 72 E12/10, 5.0V, Au, EDOMMDL11DSU-011021129.
IBM11M8735C
IBM11M8735CB
8M x 72 DRAM MODULE
Features
• 168 Pin JEDEC Standard, 8 Byte Dual In-line
Memory Module
• Optimized for ECC applications
• System Performance Benefits:
-Buffered inputs (except RAS, Data)
• 8Mx72 Dual Bank Extended Data Out Mode
DIMM
• Performance:
-Reduced noise (32 V /V pins)
SS CC
-60
-70
-4 Byte Interleave enabled
-Buffered PDs
tRAC
tCAC
tAA
RAS Access Time
60ns
20ns
35ns
70ns
25ns
40ns
CAS Access Time
• Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
Access Time From Address
tRC
Cycle Time
104ns 124ns
25ns 30ns
• Refresh Modes: RAS-Only, CBR and Hidden
Refresh
tHPC
Fast Page Mode Cycle Time
• 4096 refresh cycles distributed across 64ms
• 12/10 addressing (Row/Column)
• All inputs and outputs are LVTTL (3.3V) or TTL
(5.0V) compatible
• Single 3.3V ± 0.3V or 5.0V ± 0.5V Power Supply
• Card size: 5.25" x 1.5" x 0.354"
• DRAMS in SOJ Package
• Au contacts
Description
IBM11M8735C is an industry standard 168-pin
8-byte Dual In-line Memory Module (DIMM) which is
organized as an 8Mx72 high speed memory array,
designed with EDO DRAMs for ECC applications,
and is configured as 2 4Mx72 banks. The DIMM
uses 36 4Mx4 EDO DRAMs in SOJ packages. The
use of EDO DRAMS allows for a reduction in Page
Mode Cycle time from 40ns (Fast Page) to 25ns for
60ns DRAM modules.
Presence Detect (PD) and Identification Detect (ID)
bits provide information about the DIMM density,
addressing, performance and features. PD bits can
be dotted at the system level and activated for each
DIMM position using the PD enable (PDE) signal. ID
bits also allow detection of card features, and may
be dot-or’d at the system level to provide information
for the entire DIMM bank. For example, the system
will determine that ECC DIMMs are installed if PD8
is low (0). ID0 need not be sensed since both x72
and x80 ECC DIMMs will function in a x72 bank.
Improved system performance is provided by the
on-DIMM buffering of selected input signals. The
specified timings include all buffer, net and skew
delays, which simplifies the memory subsystem
design analysis. The data and RAS signals are not
buffered, which preserves the DRAM access specifi-
cations of 60ns and 70ns.
All IBM 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products are the x64 and x72 par-
ity (5V) DIMMs and ECC DIMMs (5V and 3.3V).
Card Outline (3.3V)
Detail A
(Front)
(Back)
1
85
10 11
94 95
84
168
40 41
124 125
See Detail A
for 5.0V Version
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8010
SA14-4635-02
Revised 5/96
Page 1 of 29
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