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IBM11M4730H-70 参数 Datasheet PDF下载

IBM11M4730H-70图片预览
型号: IBM11M4730H-70
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory IC, 4MX72, CMOS, PDMA168]
分类和应用: 光电二极管
文件页数/大小: 26 页 / 284 K
品牌: IBM [ IBM ]
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IBM11M1730BB1M  
x 72 E10/10, 3.3V, Au.  
IBM11M4730H  
IBM11M4730HB  
4M x 72 DRAM MODULE  
Features  
• Au contacts  
• 168 Pin JEDEC Standard, 8 Byte Dual In-line  
Memory Module  
• Optimized for ECC applications  
• System Performance Benefits:  
-Buffered inputs (except RAS, Data)  
• 4Mx72 (Dual Bank) Fast Page Mode DIMM  
• Performance:  
-60  
-70  
-Reduced noise (32 V /V pins)  
SS CC  
tRAC  
tCAC  
tAA  
RAS Access Time  
60ns  
20ns  
35ns  
70ns  
25ns  
40ns  
-Buffered PDs  
CAS Access Time  
• Fast Page Mode, Read-Modify-Write Cycles  
Access Time From Address  
Cycle Time  
• Refresh Modes: RAS-Only, CBR and Hidden  
Refresh  
tRC  
110ns 130ns  
40ns 45ns  
tPC  
Fast Page Mode Cycle Time  
• 2048 refresh cycles distributed across 32ms  
• 11/10 addressing (Row/Column)  
• All inputs and outputs are LVTTL (3.3V) or TTL  
(5.0V) compatible  
• Single 3.3V ± 0.3V or 5.0V ± 0.5V Power Supply  
• Card size: 5.25" x 1.5" x 0.157"  
• DRAMS in TSOP Package  
Description  
IBM11M4730H is an industry standard 168-pin  
8-byte Dual In-line Memory Module (DIMM) which is  
organized as a 4Mx72 high speed memory array,  
designed for ECC applications, and is configured as  
2 2Mx72 banks. The DIMM uses 18 2Mx8 DRAMs in  
TSOP packages.  
bits provide information about the DIMM density,  
addressing, performance and features. PD bits can  
be dotted at the system level and activated for each  
DIMM position using the PD enable (PDE) signal. ID  
bits also allow detection of card features, and may  
be dot-or’d at the system level to provide information  
for the entire DIMM bank. For example, the system  
will determine that ECC DIMMs are installed if PD8  
is low (0). ID0 need not be sensed since both x72  
and x80 ECC DIMMs will function in a x72 bank.  
Improved system performance is provided by the  
on-DIMM buffering of selected input signals. The  
specified timings include all buffer, net and skew  
delays, which simplifies the memory subsystem  
design analysis. The data and RAS signals are not  
buffered, which preserves the DRAM access specifi-  
cations of 60ns and 70ns.  
All IBM 168-pin DIMMs provide a high performance,  
flexible 8-byte interface in a 5.25” long space-saving  
footprint. Related products are the x64 and x72 par-  
ity (5V) DIMMs and ECC DIMMs (5V and 3.3V).  
Presence Detect (PD) and Identification Detect (ID)  
Card Outline (3.3V)  
Detail A  
(Front)  
(Back)  
1
85  
10 11  
94 95  
84  
168  
40 41  
124 125  
See Detail A  
for 5.0V Version  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
54H8529  
SA14-4637-01  
Released 3/96  
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