Discontinued (9/98 - last order; 3/99 last ship)
IBM11M4730C4M
x 72 E12/10, 5.0V, Au.
IBM11M2645H
IBM11M2645HB
2M x 64 DRAM MODULE
Features
• 168 Pin JEDEC Standard, 8 Byte Dual In-line
Memory Module
• System Performance Benefits:
-Buffered inputs (except RAS, Data)
• 2Mx64 Extended Data Out Page Mode DIMM
• Performance:
-Reduced noise (32 V /V pins)
SS CC
-4 Byte Interleave enabled
-Byte write, byte read accesses
-Buffered PDs
-60
-70
tRAC
tCAC
tAA
RAS Access Time
CAS Access Time
Access Time From Address
Cycle Time
60ns
20ns
35ns
70ns
25ns
40ns
• Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
• Refresh Modes: RAS-Only, CBR and Hidden
Refresh
tRC
104ns 124ns
25ns 30ns
tHPC
EDO Mode Cycle Time
• 2048 refresh cycles distributed across 32ms
• 11/10 addressing (Row/Column)
• Card size: 5.25" x 1.0" x 0.157"
• DRAMS in TSOP Package
• All inputs and outputs are LVTTL (3.3V) or TTL
(5.0V) compatible
• Single 3.3V ± 0.3V or 5.0V ± 0.5V Power Supply
• Au contacts
• Optimized for byte-write non-parity applications
Description
IBM11M2645H is an industry standard 168-pin
8-byte Dual In-line Memory Module (DIMM) which is
organized as a 2Mx64 high speed memory array
designed with EDO DRAMs for non-parity applica-
tions. The DIMM uses 8 2Mx8 EDO DRAMs in
TSOP packages. The use of EDO DRAMs allows for
a reduction in Page Mode Cycle time from 40ns
(Fast Page) to 25ns for 60ns DRAM modules.
bits provide information about the DIMM density,
addressing, performance and features. PD bits can
be dotted at the system level and activated for each
DIMM position using the PD enable (PDE) signal. ID
bits also allow detection of card features, and may
be dot-or’d at the system level to provide information
for the entire DIMM bank. For example, if a x64 par-
ity DIMM were inserted into a bank of x72 parity
DIMMs, ID0 (grounded) would indicate that at least
one DIMM in that memory bank is x64, and if the
memory controller is designed to do so, all DIMMs in
that memory bank will function as x64s.
Improved system performance is provided by the
on-DIMM buffering of selected input signals. The
specified timings include all buffer, net and skew
delays, which simplifies the memory subsystem
design analysis. The data and RAS signals are not
buffered, which preserves the DRAM access specifi-
cations of 60ns and 70ns.
All IBM 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products are the x72 parity (5V)
and ECC DIMMs (5V and 3.3V).
Presence Detect (PD) and Identification Detect (ID)
Card Outline (3.3V)
Detail A
(Front)
(Back)
1
85
10 11
94 95
84
168
40 41
124 125
See Detail A
for 5.0V Version
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H4197
SA14-4614-02
Released 5/96
Page 1 of 29
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