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IBM11M2640HB-70 参数 Datasheet PDF下载

IBM11M2640HB-70图片预览
型号: IBM11M2640HB-70
PDF下载: 下载PDF文件 查看货源
内容描述: [Fast Page DRAM Module, 2MX64, 70ns, CMOS, PDMA168]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 26 页 / 304 K
品牌: IBM [ IBM ]
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Discontinued (9/98 - last order; 3/99 last ship)  
IBM11M2640H2M  
x 6411/10, 5.0V, Au.  
IBM11M2640H  
IBM11M2640HB  
2M x 64 DRAM MODULE  
Features  
• 168 Pin JEDEC Standard, 8 Byte Dual In-line  
Memory Module  
• Optimized for byte-write non-parity applications  
• System Performance Benefits:  
• 2Mx64 Fast Page Mode DIMM  
• Performance:  
- Buffered inputs (except RAS, Data)  
- Reduced noise (32 V /V pins)  
SS CC  
- 4 Byte Interleave enabled  
- Byte write, byte read accesses  
- Buffered PDs  
-60  
-70  
tRAC  
tCAC  
tAA  
RAS Access Time  
60ns  
20ns  
35ns  
70ns  
25ns  
40ns  
CAS Access Time  
• Fast Page Mode, Read-Modify-Write Cycles  
Access Time From Address  
Cycle Time  
• Refresh Modes: RAS-Only, CBR and Hidden  
Refresh  
tRC  
110ns 130ns  
40ns 45ns  
tPC  
Fast Page Mode Cycle Time  
• 2048 refresh cycles distributed across 32ms  
• 11/10 addressing (Row/Column)  
• Card size: 5.25" x 1.0" x 0.157"  
• DRAMS in TSOP Package  
• All inputs and outputs are LVTTL (3.3V) or TTL  
(5.0V) compatible  
• Single 3.3V ± 0.3V or 5V ± 0.5V Power Supply  
• Au contacts  
Description  
IBM11M2640H is an industry standard 168-pin  
8-byte Dual In-line Memory Module (DIMM) which is  
organized as a 2Mx64 high speed memory array for  
non-parity applications. The DIMM uses 8 2Mx8  
DRAMs in TSOP packages.  
be dotted at the system level and activated for each  
DIMM position using the PD enable (PDE) signal. ID  
bits also allow detection of card features, and may  
be dot-or’d at the system level to provide information  
for the entire DIMM bank. For example, if a x64 par-  
ity DIMM were inserted into a bank of x72 parity  
DIMMs, ID0 (grounded) would indicate that at least  
one DIMM in that memory bank is x64, and if the  
memory controller is designed to do so, all DIMMs in  
that memory bank will function as x64s.  
Improved system performance is provided by the  
on-DIMM buffering of selected input signals. The  
specified timings include all buffer, net and skew  
delays, which simplifies the memory subsystem  
design analysis. The data and RAS signals are not  
buffered, which preserves the DRAM access specifi-  
cations of 60ns and 70ns.  
All IBM 168-pin DIMMs provide a high performance,  
flexible 8-byte interface in a 5.25” long space-saving  
footprint. Related products are the x72 parity (5V)  
and ECC DIMMs (5V and 3.3V).  
Presence Detect (PD) and Identification Detect (ID)  
bits provide information about the DIMM density,  
addressing, performance and features. PD bits can  
Card Outline (3.3V)  
Detail A  
(Front)  
(Back)  
1
85  
10 11  
94 95  
84  
168  
40 41  
124 125  
See Detail A  
for 5.0V Version  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
64G1559  
SA14-4612-04  
Revised 5/96