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IBM11M18845CB-5RT 参数 Datasheet PDF下载

IBM11M18845CB-5RT图片预览
型号: IBM11M18845CB-5RT
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM Module, 16MX72, 50ns, CMOS, DIMM-168]
分类和应用: 动态存储器内存集成电路
文件页数/大小: 29 页 / 347 K
品牌: IBM [ IBM ]
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Discontinued (7/00 - last order; 9/00 - last ship)  
IBM11M8730HB8M  
x 72 E12/11, 3.3V, Au.  
IBM11M16845CB  
Preliminary  
Features  
• 168 Pin JEDEC Standard, 8 Byte Dual In-line  
Memory Module  
16M x 72 Chipkill Correct DRAM Module  
• Optimized for ECC applications  
• System Performance Benefits:  
- Buffered inputs (except RAS, Data)  
• 16Mx72 Chipkill Correct EDO DIMM  
• Performance:  
- Reduced noise (32 V /V pins)  
SS CC  
- Buffered PDs  
-5R  
-6R  
• Extended Data Out (EDO) Mode, Read-Modify-  
Write Cycles  
• Refresh Modes: RAS-Only, CBR and Hidden  
Refresh  
• 4096 refresh cycles distributed across 64ms  
(CBR)  
• 13/11 addressing (Row/Column)  
• Card size: 5.25" x 1.9" x 0.157"  
• DRAMS in TSOP Package  
50ns  
19ns  
34ns  
89ns  
20ns  
60ns  
22ns  
37ns  
104ns  
25ns  
tRAC  
tCAC  
tAA  
RAS Access Time  
CAS Access Time  
Access Time From Address  
Cycle Time  
tRC  
EDO Mode Cycle Time  
tHPC  
• All inputs and outputs are LVTTL compatible  
• Single 3.3 ± 0.15V Power Supply  
• Au contacts  
Description  
IBM11M16845CB is an industry standard 168-pin  
8-byte Dual In-line Memory Module (DIMM) which is  
organized as a 16Mx72 high speed memory array,  
designed with EDO DRAMs for ECC applications.  
The DIMM uses additional checkbit DRAMs and an  
ASIC to provide chipkill correction when deployed in  
existing single-error-correct ECC systems.  
Presence Detect (PD) and Identification Detect (ID)  
bits provide information about the DIMM density,  
addressing, performance and features. PD bits can  
be dotted at the system level and activated for each  
DIMM position using the PD enable (PDE) signal. ID  
bits also allow detection of card features, and may  
be dot-or’d at the system level to provide information  
for the entire DIMM bank.  
Improved system performance is provided by the  
on-DIMM buffering of selected input signals. The  
specified timings include all buffer, net and skew  
delays, which simplifies the memory subsystem  
design analysis. The data and RAS signals are not  
buffered, which preserves the DRAM access specifi-  
cation of 50ns or 60ns.  
All IBM 168-pin DIMMs provide a high performance,  
flexible 8-byte interface in a 5.25" long space-saving  
footprint. Related products are the x64 and x72 par-  
ity (5V) DIMMs and ECC DIMMs (5V and 3.3V).  
Card Outline  
(Front)  
(Back)  
1
85  
10 11  
94 95  
84  
168  
40 41  
124 125  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
01L5991.00  
Rev 12/97