IBM0625164GT3B IBM0625404GT3B
IBM06254B4GT3B IBM0625804GT3B
Advance
256Mb Double Data Rate Synchronous DRAM
Features
CAS Latency and Frequency
• DLL aligns DQ and DQS transitions with CK
transitions, also aligns QFC transitions with CK
Maximum Operating Frequency (MHz)*
CAS Latency
during Read cycles
PC266A
133
PC266B
125
PC200
100
2
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
2.5
143
133
125
* Values are nominal (exact tCK should be used).
• Burst lengths: 2, 4, or 8
• Double data rate architecture: two data transfers
per clock cycle
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• Bidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiver
• 7.8ns Maximum Average Periodic Refresh
Interval
• DQS is edge-aligned with data for reads and is
center-aligned with data for writes
• 2.5V (SSTL_2 compatible) I/O
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• V
= 2.5V ± 0.2V
DDQ
• V = 2.5V ± 0.2V
DD
Description
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
268,435,456 bits. It is internally configured as a
quad-bank DRAM.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with
the registration of an Active command, which is then
followed by a Read or Write command. The address
bits registered coincident with the Active command
are used to select the bank and row to be accessed.
The address bits registered coincident with the
Read or Write command are used to select the bank
and the starting column location for the burst
access.
The 256Mb DDR SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O
pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit
wide, one clock cycle data transfer at the internal
DRAM core and two corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins.
The DDR SDRAM provides for programmable Read
or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst access.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the
DDR SDRAM during Reads and by the memory
controller during Writes. DQS is edge-aligned with
data for Reads and center-aligned with data for
Writes.
As with standard SDRAMs, the pipelined, multibank
architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective band-
width by hiding row precharge and activation time.
The 256Mb DDR SDRAM operates from a differen-
tial clock (CK and CK; the crossing of CK going
HIGH and CK going LOW is referred to as the posi-
tive edge of CK). Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and
output data is referenced to both edges of DQS, as
well as to both edges of CK.
An auto refresh mode is provided along with a
power-saving power-down mode. All inputs are
compatible with the JEDEC Standard for SSTL_2.
All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
29L0011.E36997
10/99
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