.
IBM0418A81XLAB
IBM0418A41XLAB
IBM0436A81XLAB
IBM0436A41XLAB
Preliminary 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• Registered Outputs
• Common I/O
• 0.25 Micron CMOS technology
• Asynchronous Output Enable and Power Down
Inputs
• Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
• Boundary Scan using limited set of JTAG
1149.1 functions
• Single Differential HSTL Clock
• +2.5V Power Supply, Ground, 1.6V V
, and
• Byte Write Capability and Global Write Enable
DDQ
0.95V V
REF
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
• HSTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
• Programmable Impedance Output Drivers
Description
The 4Mb and 8Mb SRAMS—IBM0436A41XLAB,
IBM0418A41XLAB, IBM0418A81XLAB, and
IBM0436A81XLAB—are Synchronous Pipeline
Mode, high-performance CMOS Static Random
Access Memories that are versatile, have wide I/O,
and can achieve 3ns cycle times. Differential K
clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Data Outs are updated from output regis-
ters off the next rising edge of the K clock. An inter-
nal Write buffer allows write data to follow one cycle
after addresses and controls. The chip is operated
with a single +2.5V power supply and is compatible
with HSTL I/O interfaces.
crrh2516.04
12/00
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