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IBM04368CBLBC
IBM04188CBLBC
8Mb (256K x 36 & 512K x 18) SRAM
Features
• 256K x 36 or 512K x 18 organization
• CMOS technology
• Registered addresses, controls, and data-ins
• Burst mode of operation
• Double-data-rate (DDR) and single-data-rate
(SDR) synchronous mode of operation
• Common I/O
• Asynchronous output enable
• Pipeline mode of operation
• Boundary scan using a limited set of JTAG
1149.1 functions
• Self-timed late write with full data coherence
• Single differential high-speed transceiver logic
(HSTL) clock with HSTL input and output levels
• 9 x 17 bump ball grid array package with SRAM
JEDEC standard pinout and boundary SCAN
order
• 2.5V power supply, 1.8V V
DDQ
• Programmable impedance output driver
Description
The IBM04368CBLBC and IBM04188CBLBC 8Mb
SRAMs are synchronous pipeline-mode, high-per-
formance CMOS static random-access memories
that have wide I/O and achieve 2.5ns cycle times.
Single differential CK clocks are used to initialize the
read/write operation; all internal operations are self-
timed. At the rising edge of the CK clock, addresses
and controls are registered internally. Data-outs are
updated from output registers on the next rising and
falling edges of the CK clock, hence the double data
rate. Internal write buffers allow write data to follow
one cycle after addresses and controls. The SRAM
is operated with a single 2.5V power supply and is
compatible with HSTL I/O interfaces.
CBLBC_ds.fm.00
June 7, 2002
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