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IBM043616CXLBC
IBM041816CXLBC
16Mb (512K x 36 & 1M x 18) SRAM
Features
• 512K x 36 or 1M x 18 organization
• 2.5V power supply, 1.5 V
DDQ
• CMOS technology
• Registered addresses, controls, and data-ins
• Common I/O
• Double-data-rate and single-data-rate synchro-
nous modes of operation
• Asynchronous output enable
• Pipeline mode of operation
• Boundary scan using a limited set of JTAG
1149.1 functions
• Burst mode of operation
• Self-timed late write with full data coherency
• 9 x 17 bump ball grid array package with SRAM
JEDEC standard pinout and boundary SCAN
order
• Single differential high-speed transceiver logic
(HSTL) clock with HSTL input and output levels
• Programmable impedance output driver
Description
The IBM043616CXLBC and IBM041816CXLBC
16Mb SRAMs are double-data-rate (DDR) pipeline
mode, high-performance CMOS static random-
access memories that have wide I/O and offer cycle
times as low as 2.5ns. Single differential CK clocks
are used to initialize the read/write operation, and all
internal operations are self-timed. In DDR mode,
every rising edge of the CK clock addresses and
controls are registered internally. Data-ins are regis-
tered on rising and falling edges of the CK clock.
Data-outs are updated from output registers on the
next rising and falling edges of the CK clock, hence
the double data rate. Internal write buffers allow
write data to follow one cycle after addresses and
controls. The SRAM is operated with a single 2.5V
power supply and is compatible with HSTL I/O inter-
faces.
CXLBCds.fm.00
June 3, 2002
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