.
IBM0418A4ACLAB IBM0418A8ACLAB
IBM0436A8ACLAB IBM0436A4ACLAB
Preliminary 8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
• 256K x 36 or 512K x 18 organizations
• 128K x 36 or 256K x 18 organizations
• Latched Outputs
• Common I/O
• 0.25 Micron CMOS technology
• Asynchronous Output Enable and Power Down
Inputs
• Synchronous Register-Latch Mode of Operation
with Self-Timed Late Write
• Boundary Scan using limited set of JTAG
1149.1 functions
• Single Differential HSTL Clock
• Byte Write Capability & Global Write Enable
• +3.3V Power Supply, Ground, 2.0Volt max
V
and 0.85Volt V
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
DDQ,
REF
• HSTL Input and Output levels,
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins.
• Programmable Impedance Output Drivers
Description
The 4 and 8Mb SRAMS—IBM0436A4ACLAB, IBM0436A8ACLAB, IBM0418A4ACLAB, and
IBM0418A8ACLAB—are Synchronous Register-Latch Mode, high-performance CMOS Static Random
Access Memories that are versatile, have wide I/O, and can achieve 3.8 ns cycle times. Differential K clocks
are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of the
K clock, all Addresses, Write-Enables, Sync Select, and Data Ins are registered internally. Data Outs are
updated from output registers off the falling edge of the K clock. An internal Write buffer allows write data to
follow one cycle after addresses and controls. The chip is operated with a single +3.3V power supply and is
compatible with HSTL I/O interfaces.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
crlh3320. 01
7/99
Page 1 of 6
IBM [ IBM ]
