.
IBM0418A8CBLBB IBM0436A8CBLBB
IBM0418A4CBLBB IBM0436A4CBLBB
Preliminary
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18)
Features
• 8Mb: 256K x 36 or 512K x 18 Organizations
4Mb: 128K x 36 or 256K x 18 Organizations
• HSTL Input and Output levels
• Registered Addresses, Controls and Data Ins
• Burst Mode of operation
• CMOS Technology
• Double Data Rate and Single Data Rate Syn-
chronous Modes of Operation
• Common I/O
• Asynchronous Output Enable
• Pipeline Mode of Operation
• Boundary Scan using limited set of JTAG
1149.1 functions
• Self-Timed Late Write with Full Data Coherency
• Single Differential HSTL Clock
• 9 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
• +2.5V Power Supply, Ground, 1.9V VDDQ, and
0.95V VREF
• Programmable Impedance Output Drivers
• PBGA Package
Description
The IBM0436A4CBLBB, IBM0418A4CBLBB,
IBM0418A8CBLBB, and IBM0436A8CBLBB
clock, all Addresses, Controls, and Data Ins are reg-
istered internally. Data Outs are updated from out-
put registers off the next rising and falling edge of
the K clock, hence the Double Data Rate. Internal
Write buffers allow write data to follow one cycle
after addresses and controls. The chip is operated
with a single +2.5V power supply and is compatible
with HSTL I/O interfaces.
SRAMS are Synchronous Pipeline Mode, high-per-
formance CMOS Static Random Access Memories
that are versatile, have wide I/O, and achieve 3.0ns
cycle times. Differential CK clocks are used to ini-
tiate the read/write operation and all internal opera-
tions are self-timed. At the rising edge of the CK
cddrh2519.04
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