.
IBM0418A4ACLAA IBM0418A8ACLAA
IBM0436A8ACLAA IBM0436A4ACLAA
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• Latched Outputs
• Common I/O
• 0.25 Micron CMOS technology
• Asynchronous Output Enable and Power Down
Inputs
• Synchronous Register-Latch Mode of Operation
with Self-Timed Late Write
• Boundary Scan using limited set of JTAG
1149.1 functions
• Single Differential HSTL Clock
• +3.3V Power Supply, Ground, 2.0 Volt max
• Byte Write Capability & Global Write Enable
V
and 0.85 Volt V
DDQ,
REF
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
• HSTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
• Programmable Impedance Output Drivers
Description
The 4Mb and 8Mb SRAMS—IBM0436A4ACLAA,
IBM0436A8ACLAA, IBM0418A4ACLAA, and
ing edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Data Outs are updated from output regis-
ters off the falling edge of the K clock. An internal
Write buffer allows write data to follow one cycle
after addresses and controls. The device is oper-
ated with a single +3.3V power supply and is com-
patible with HSTL I/O interfaces.
IBM0418A8ACLAA—are Synchronous Register-
Latch Mode, high-performance CMOS Static Ran-
dom Access Memories that are versatile, have wide
I/O, and can achieve 4.2 ns cycle times. Differential
K clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
trlh3320.04
01/01
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Use is further subject to the provisions at the end of this document.
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