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IBM04188ETLAC
IBM04368ETLAC
8Mb (256K x 36 & 512K x 18) SRAM
Features
• Common I/O
• 256K x 36 or 512K x 18 organization
• CMOS technology
• Asynchronous output enable and sleep mode
inputs
• Synchronous late-select mode of operation with
self-timed late write
• Boundary scan using a limited set of JTAG
1149.1 functions
• Single differential high-speed transceiver logic
(HSTL) clock
• Byte write capability and global write enable
• 7 x 17 bump ball grid array package with SRAM
JEDEC standard pinout and boundary scan
order
• 3.3V power supply, 1.5V V
DDQ
• HSTL input and output levels
• Registered addresses, write enables, synchro-
nous select and data-ins.
• Programmable impedance output drivers
Description
The 3.3V IBM04188ETLAC and IBM04368ETLAC
SRAMs are synchronous pipeline-mode, late select,
high-performance CMOS static random-access
memories that have wide I/O and achieve 3ns cycle
times. Single differential K clocks are used to initiate
the read/write operation, and all internal operations
are self-timed. At the rising edge of the K clock, all
addresses, write-enables, synchronous select, and
data-ins are registered internally. Data-outs are
updated from output registers on the next rising
edge of the K clock. An internal write buffer allows
write data to follow one cycle after addresses and
controls. Address SAS is a late-select address. It
performs a one-of-two decode on the data
addressed by addresses SA1–SA18 in the previous
cycle. The SRAM is operated with a single 3.3V
power supply and is compatible with 1.5V HSTL I/O
interfaces.
ETLAC_ds.fm.00
June 07, 2002
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