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IBM0436166XLAC
IBM0418166XLAC
Preliminary
Features
16Mb (512K x 36 & 1M x 18) SRAM
• 512K × 36 or 1M × 18 organization
• Common I/O
• CMOS technology
• Asynchronous output enable and sleep mode
inputs
• Synchronous pipeline mode of operation with
self-timed late write
• Boundary scan using a limited set of JTAG
1149.1 functions
• Single differential HSTL clock
• HSTL input and output levels
• +2.5V power supply
• Byte write capability and global write enable
• 7 × 17 bump ball grid array (BGA) package with
SRAM JEDEC standard pinout and boundary
scan order
• Registered addresses, write enables, synchro-
nous select, and data-ins
• Programmable impedance output drivers
Description
The IBM0418166XLAC and IBM0436166XLAC
16Mb SRAMS are synchronous pipeline mode, high-
performance CMOS static random-access memo-
ries that have wide I/O and achieve 2-ns cycle times.
Single differential K clocks are used to initiate the
read/write operation, and all internal operations are
self-timed. At the rising edge of the K clock, all
addresses, write enables, synchronous selects, and
data-ins are registered internally. Data-outs are
updated from output registers off the next rising
edge of the K clock. An internal write buffer allows
write data to follow one cycle after addresses and
controls. The chip is operated with a single +2.5V
power supply and is compatible with HSTL I/O inter-
faces.
XLACds.fm.00
November 24, 2003
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