Discontinued (8/99 - last order; 12/99 - last ship)
IBM036440416M
x 412/10/2, 3.3V 72. IBM03644B432M x 412/10/2, 3.3V 72. IBM03641644M x 1612/8/2, 3.3V 72. IBM03648048M x 412/9/2, 3.3V 72.
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Features
• Programmable Wrap: Sequential or Interleave
• High Performance:
• Multiple Burst Read with Single Write Option
-68, -260, -360, -10,
CL=3 CL=3 CL=3 CL=3
Units
• Automatic and Controlled Precharge Command
fCK
tCK
tAC
tAC
Clock Frequency
Clock Cycle
147
6.8
6
135
7.4
—
135
7.4
—
100 MHz
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard or Low Power operation
• 4096 refresh cycles/64ms
10
7
ns
ns
ns
1
2
Clock Access Time
Clock Access Time
—
6
6
9
1. Terminated load. See AC Characteristics on page 44.
2. Unterminated load. See AC Characteristics on page 44.
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Random Column Address every CLK (1-N Rule)
• Single 3.3V ± 0.3V Power Supply
• LVTTL compatible
• Four Banks controlled by A12/A13 (Bank
Select)
• Programmable CAS Latency: 2, 3
• Package: 54-pin 400 mil TSOP-Type II
2 High Stack TSOJ
• Programmable Burst Length: 1, 2, 4, 8, full-page
Description
The IBM0364404, IBM0364804, and IBM0364164
are four-bank Synchronous DRAMs organized as
4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and
1Mbit x 16 I/O x 4 Bank, respectively. IBM03644B4,
a stacked version of the x4 component, is also
offered. These synchronous devices achieve high-
speed data transfer rates of up to 147MHz by
employing a pipeline chip architecture that synchro-
nizes the output data to a system clock. The chip is
fabricated with IBM’s advanced 64Mbit single tran-
sistor CMOS DRAM process technology.
and two bank select addresses (A12, A13) are
strobed with RAS. Ten column addresses (A0-A9)
plus bank select addresses and A10 are strobed
with CAS. Column address A9 is dropped on the x8
device and column addresses A8 and A9 are
dropped on the x16 device. Access to the lower or
upper DRAM in a stacked device is controlled by
CS0 and CS1, respectively.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A13
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
The device is designed to comply with all JEDEC
standards for synchronous DRAM products, both
electrically and mechanically. All the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 147MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Simultaneous oper-
ation of both decks of a stacked device is allowed,
depending on the operation being done.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CLK). Internal chip operating modes
are defined by combinations of these signals, and a
command decoder initiates the necessary timings
for each operation. A fourteen-bit address bus
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
Auto Refresh (CBR), Self Refresh, and Low Power
operation are supported.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 1 of 72
IBM [ IBM ]
