IBM0316409C 4M
x 412/10, 3.3V, SR. IBM0316169C 1M x 1612/8, 3.3V, SR. IBM0316809C 2M x 812/9, 3.3V, SR.
IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
Features
• High Performance:
CAS latency = 3
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4,x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 refresh cycles/64ms
-10 -11 -12 -13 Units
fCK
tCK3
tAC3
Clock Frequency
Clock Cycle
100 91
83
12
11
77
13
12
MHz
ns
10
9
11
10
Clock Access Time
ns
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Dual Banks controlled by A11 (Bank Select)
• Programmable CAS Latency: 1,2,3
• Random Column Address every CLK (1-N Rule)
• Single 3.3V ± 0.3V Power Supply
• Programmable Burst Length: 1,2,4,8,full-page
• LVTTL compatible
• Programmable Wrap Sequence: Sequential or
Interleave
• Package: 40 pin 400 mil TSOP-Type II (x4,x8)
50 pin 400 mil TSOP-Type II (x16)
Description
The
IBM0316409C,
IBM0316809C,
and
addresses (A0-A10) and a bank select address
(A11) are strobed with RAS. Ten column addresses
(A0-A9) plus a bank select address (A11) are
strobed with CAS. Column address A9 is dropped
on the x8 device and column addresses A8 and A9
are dropped on the x16 device.
IBM0316169C are dual bank Synchronous DRAM’s
organized as 2Mbit x 4 I/O x 2 Bank, 1Mbit x 8 I/O x
2 Bank, and 512Kbit x 16 I/O x 2 Bank, respectively.
These synchronous devices achieve high speed
data transfer rates of up to 100MHz by employing a
chip architecture that prefetches multiple bits and
then synchronizes the output data to a system clock.
The chip is fabricated with IBM’s advanced 16Mbit
single transistor CMOS DRAM process technology.
The device is designed to comply with all
JEDEC standards set for synchronous DRAM prod-
ucts, both electrically and mechanically. All of the
control, address and data input/output circuits are
synchronized with the positive edge of an externally
supplied clock.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A9
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
Operating the two memory banks in an inter-
leave fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
100MHz is possible depending on burst length, CAS
latency, and speed grade of the device.
RAS, CAS, WE, and CS are pulsed signals
which are examined at the positive edge of each
externally applied clock (CLK). Internal chip operat-
ing modes are defined by combinations of these sig-
Auto Refresh (CBR) and Self Refresh operation
are supported. These devices operate with a single
3.3V ± 0.3V power supply and are available in
400mil TSOP Type II packages.
nals and
a
command decoder initiates the
necessary timings for each operation. A twelve bit
address bus accepts address data in the conven-
tional RAS/CAS multiplexing style. Eleven row
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 1 of 100
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