IBM0144051M
x 410/10, 5.0V, EDO. IBM014405P1M x 410/10, 3.3V, EDO, LP, SR. IBM014405M1M x 410/10, 5.0V, EDO, LP, SR. IBM014405B1M x 410/10, 3.3V, EDO.
IBM014405 IBM014405M
IBM014405B IBM014405P
1M x 4 10/10 EDO DRAM
Features
• 1,048,576 word by 4 bit organization
• Low Power Dissipation
- Active (max)
- 95 mA / 80 mA (3.3V)
• Power Supply: 3.3V ± 0.3V or 5.0V ± 0.5V
• Extended Data Out (Hyper Page) Mode
• Standard Power (SP) and Low Power (LP)
- 85 mA / 70 mA (5.0V)
- Standby Current: TTL Inputs (max)
- 2.0 mA (SP version)
- 1.0 mA (LP version)
• 1024 Refresh Cycles
- 16 ms Refresh Rate (SP version)
- Standby Current: CMOS Inputs (max)
- 1.0 mA (SP version)
- 128 ms Refresh Rate (LP version)
- 0.15 mA (LP version)
• High Performance:
• RAS Only Refresh
Parameter
RAS Access Time
-60
-70
• CAS before RAS Refresh
• Hidden Refresh
tRAC
tCAC
tAA
60 ns 70 ns
15 ns 18 ns
30 ns 35 ns
104 ns 124 ns
CAS Access Time
Column Address Access Time
Cycle Time
• Self Refresh (LP version only)
• Packages: SOJ-26/20 (300mil)
TSOP-26/20 (300mil)
tRC
tHPC
EDO (Hyper Page) Mode Cycle Time 25 ns 30 ns
Description
The IBM014405 is an Extended Data Out (Hyper
Page) Mode dynamic RAM organized 1,048,576
words by 4 bits. The devices are fabricated in IBM’s
4M-bit Shrink 3 CMOS silicon gate technology. The
circuits and process have been designed to provide
high performance, low power dissipation, and high
reliability. The devices operate with either a 5.0V ±
0.5V or 3.3V ± 0.3V power supply and are offered in
a plastic 26/20 pin 300mil SOJ or TSOP package.
Refreshing may be accomplished by means of a
CAS before RAS refresh cycle (CBR) that internally
generates the refresh address. RAS - only refresh
cycles can also refresh all memory locations. Self-
Refresh mode is included as a standard feature for
the Low Power devices (IBM014405M and
IBM014405P). All low power devices support
Extended Data Retention of 128 ms, eight times (8x)
the retention supported by IBM’s standard power
devices.
Pin Assignments
Pin Description
A0 - A9
I/O0 - I/O3
RAS
Address Input
26
25
24
23
22
Vss
I/O3
I/O2
CAS
OE
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
Data Input/Output
Row Address Strobe
Column Address Strobe
Read/Write Enable
Output Enable
CAS
WE
OE
VCC
Power (5.0 V or 3.3V)
Ground
A0
A1
A2
A3
Vcc
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6242
SA14-4232-03
Revised 6/96
Page 1 of 29
IBM [ IBM ]
