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IBM0118165MT3-50 参数 Datasheet PDF下载

IBM0118165MT3-50图片预览
型号: IBM0118165MT3-50
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 1MX16, 50ns, CMOS, PDSO44, 0.400 X 0.825 INCH, TSOP2-50/44]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 31 页 / 350 K
品牌: IBM [ IBM ]
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IBM0118165 IBM0118165M  
IBM0118165B IBM0118165P  
1M x 16 10/10 EDO DRAM  
Features  
• Low Power Dissipation  
• 1,048,576 word by 16 bit organization  
- Active (max) - 185 mA / 165 mA / 140 mA  
- Standby: TTL Inputs (max) - 1.0 mA  
- Standby: CMOS Inputs (max)  
- 1.0 mA (SP version)  
• Single 3.3V ± 0.3V or 5.0V ± 0.5V power supply  
• Standard Power (SP) and Low Power (LP)  
- 0.2 mA (LP version)  
- Self Refresh (LP version only)  
- 200µA (3.3 Volt)  
• 1024 Refresh Cycles  
- 16 ms Refresh Rate (SP version)  
- 128 ms Refresh Rate (LP version)  
- 300µA (5.0 Volt)  
• High Performance:  
• Extended Data Out (Hyper Page) Mode  
• Dual CAS Byte Read/Write  
• Read-Modify-Write  
-50 -60 -6R -70 Units  
tRAC  
tCAC  
tAA  
RAS Access Time  
CAS Access Time  
50 60 60 70  
13 15 17 20  
ns  
ns  
ns  
• RAS Only and CAS before RAS Refresh  
• Hidden Refresh  
Column Address Access Time 25 30 30 35  
tRC  
Cycle Time  
84 104 104 124 ns  
20 25 25 30 ns  
EDO (Hyper Page) Mode  
Cycle Time  
• Package: TSOP-II 50/44 (400milx825mil)  
SOJ 42/42 (400mil)  
tHPC  
Description  
vide high performance, low power dissipation, and  
high reliability. The devices operate with a single  
3.3V ± 0.3V or 5.0V ± 0.5V power supply. The 20  
addresses required to access any bit of data are  
multiplexed (10 are strobed with RAS, 10 are  
strobed with CAS).  
The IBM0118165 is a dynamic RAM organized  
1,048,576 words by 16 bits, which has a very low  
“sleep mode” power consumption option. These  
devices are fabricated in IBM’s advanced 0.5µm  
CMOS silicon gate process technology. The circuit  
and process have been carefully designed to pro-  
Pin Assignments (Top View)  
Pin Description  
RAS  
LCAS / UCAS  
WE  
Row Address Strobe  
L/U Column Address Strobe  
Read/Write Input  
Address Inputs  
50/44 TSOP  
42/42 SOJ  
VCC  
IO0  
IO1  
IO2  
IO3  
VCC  
IO4  
IO5  
IO6  
IO7  
NC  
1
50  
VSS  
VCC  
IO0  
IO1  
IO2  
IO3  
VCC  
IO4  
IO5  
IO6  
IO7  
1
2
3
4
5
6
7
8
42  
VSS  
2
3
4
5
49 IO15  
48 IO14  
47 IO13  
46 IO12  
41 IO15  
40 IO14  
39 IO13  
38 IO12  
A0 - A9  
OE  
Output Enable  
6
7
8
9
10  
11  
45  
VSS  
37  
VSS  
44 IO11  
43 IO10  
42 IO9  
41 IO8  
40 NC  
36 IO11  
35 IO10  
34 IO9  
I/O0 - I/O15  
VCC  
Data Input/Output  
Power (+3.3V or +5.0V)  
Ground  
9
33  
32 NC  
IO8  
10  
11  
VSS  
NC  
NC  
NC  
WE  
RAS  
NC  
NC  
A0  
A1  
A2  
A3  
VCC  
15  
16  
17  
18  
19  
20  
21  
22  
23  
36 NC  
35 LCAS  
34 UCAS  
33 OE  
32 A9  
31 A8  
30 A7  
29 A6  
28 A5  
27 A4  
NC  
WE  
RAS  
NC  
NC  
A0  
12  
13  
14  
15  
16  
17  
18  
19  
31 LCAS  
30 UCAS  
29 OE  
28 A9  
27 A8  
26 A7  
A1  
A2  
25 A6  
24 A5  
A3  
VCC  
20  
21  
23 A4  
24  
25  
22  
VSS  
26  
VSS  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
28H4721  
SA14-4223-04  
Revised 11/96  
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