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IBM0118160PT3-70 参数 Datasheet PDF下载

IBM0118160PT3-70图片预览
型号: IBM0118160PT3-70
PDF下载: 下载PDF文件 查看货源
内容描述: [Fast Page DRAM, 1MX16, 70ns, CMOS, PDSO44, 0.400 X 0.825 INCH, TSOP2-50/44]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 27 页 / 280 K
品牌: IBM [ IBM ]
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IBM0118160 1M  
x 1610/10, 5.0V. IBM0118160P1M x 1610/10, 3.3V, LP, SR. IBM0118160M 1M x 1610/10, 5.0V, LP, SR. IBM0118160B1M x 1610/10, 3.3V.  
IBM0118160 IBM0118160M  
IBM0118160B IBM0118160P  
1M x 16 10/10 DRAM  
Features  
• Low Power Dissipation  
• 1,048,576 word by 16 bit organization  
- Active (max) - 185 mA / 160 mA / 140 mA  
- Standby: TTL Inputs (max) - 2.0 mA  
- Standby: CMOS Inputs (max)  
- 1.0 mA (SP version)  
• Single 3.3V ± 0.3V or 5.0V ± 0.5V power supply  
• Standard Power (SP) and Low Power (LP)  
- 0.2 mA (LP version)  
- Self Refresh (LP version only)  
- 200µA (3.3 Volt)  
• 1024 Refresh Cycles  
- 16 ms Refresh Rate (SP version)  
- 128 ms Refresh Rate (LP version)  
- 300µA (5.0 Volt)  
• High Performance:  
• 2 CAS  
-50  
-60  
-70  
• Read-Modify-Write  
tRAC  
tCAC  
tAA  
RAS Access Time  
50ns  
13ns  
25ns  
60ns  
15ns  
30ns  
70ns  
20ns  
35ns  
• RAS Only and CAS before RAS  
• Hidden Refresh  
CAS Access Time  
Column Address Access Time  
Cycle Time  
• Package:  
tRC  
95ns 110ns 130ns  
35ns 40ns 45ns  
- TSOP-II 50/44 (400milx825mil)  
- SOJ 42/42 (400mil)  
tPC  
Fast Page Mode Cycle Time  
Description  
vide high performance, low power dissipation, and  
high reliability. The devices operate with a single  
3.3V ± 0.3V or 5.0V ± 0.5V power supply. The 20  
addresses required to access any bit of data are  
multiplexed (10 are strobed with RAS, 10 are  
strobed with CAS).  
The IBM0118160 is a dynamic RAM organized  
1,048,576 words by 16 bits, which has a very low  
“sleep mode” power consumption option. These  
devices are fabricated in IBM’s advanced 0.5µm  
CMOS silicon gate process technology. The circuit  
and process have been carefully designed to pro-  
Pin Assignments (Top View)  
Pin Description  
RAS  
LCAS / UCAS  
WE  
Row Address Strobe  
L/U Column Address Strobe  
Read/Write Input  
Address Inputs  
50/44 TSOP  
42/42 SOJ  
VCC  
IO0  
IO1  
IO2  
IO3  
VCC  
IO4  
IO5  
IO6  
IO7  
NC  
1
50  
VSS  
VCC  
IO0  
IO1  
IO2  
IO3  
VCC  
IO4  
IO5  
IO6  
IO7  
1
2
3
4
5
6
7
8
42  
VSS  
2
3
4
5
49 IO15  
48 IO14  
47 IO13  
46 IO12  
41 IO15  
40 IO14  
39 IO13  
38 IO12  
A0 - A9  
OE  
Output Enable  
6
7
8
9
10  
11  
45  
VSS  
37  
VSS  
44 IO11  
43 IO10  
42 IO9  
41 IO8  
40 NC  
36 IO11  
35 IO10  
34 IO9  
33 IO8  
32 NC  
I/O0 - I/O15  
VCC  
Data Input/Output  
Power (+3.3V or +5.0V)  
Ground  
9
10  
VSS  
NC  
11  
NC  
NC  
WE  
RAS  
NC  
NC  
A0  
A1  
A2  
A3  
VCC  
15  
16  
17  
18  
19  
20  
21  
22  
23  
36 NC  
35 LCAS  
34 UCAS  
33 OE  
32 A9  
31 A8  
30 A7  
29 A6  
28 A5  
27 A4  
NC  
WE  
RAS  
NC  
NC  
A0  
12  
13  
14  
15  
16  
17  
18  
19  
31 LCAS  
30 UCAS  
29 OE  
28 A9  
27 A8  
26 A7  
A1  
A2  
25 A6  
24 A5  
A3  
VCC  
20  
21  
23 A4  
24  
25  
22  
VSS  
26  
VSS  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
43G9388  
SA14-4209-04  
Revised 11/96  
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