IBM0116400M 4M
x 412/10, 5.0V, LP, SR. IBM0116400P 4M x 412/10, 3.3V, LP, SR.
IBM01164B0
IBM01164D0
4M x 4 Stacked DRAM
Features
• 4,194,304 word by 4 bit organization by 2 High
• 4,194,304 word by 4 bit organization by 4 High
• Single 3.3V or 5.0V power supply
• 4096 refresh cycles 64ms
• Low Power Dissipation (per deck)
- Active (max) - 85mA/75mA
- Standby (TTL Inputs) - 1.0mA (max)
- Standby (CMOS Inputs) - 1.0mA (max)
• Fast Page Mode
• Read-Modify-Write
• High Performance:
• CAS before RAS Refresh
• RAS only Refresh
-60
-70
tRAC
tCAC
RAS Access Time
CAS Access Time
60ns
15ns
70ns
20ns
• Hidden Refresh
• Package: TSOJ-32 (400mil x 825mil)
Column Address
Access Time
tAA
tRC
tPC
30ns
110ns
40ns
35ns
130ns
45ns
Cycle Time
Fast Page Mode Cycle
Time
Description
mance, low power dissipation, and high reliability.
The devices operate with a single 3.3V or 5.0V
power supply. The 22 addresses required to access
any bit of data are multiplexed (12 are strobed with
RAS, 10 are strobed with CAS). The 2 High requires
2 RAS pins and the 4 High requires 4 RAS pins.
The IBM01164B0 and IBM01164D0 are dynamic
RAMS organized 4,194,304 words by 4 bits in 2 high
or 4 high stacks, respectively. These devices are
fabricated in IBM’s advanced 0.5µm CMOS silicon
gate process technology. The circuit and process
have been carefully designed to provide high perfor-
Pin Assignments (Top View)
Pin Description
RAS0-RAS1
RAS0-RAS3
CAS
Row Address Strobe- 2 High
Row Address Strobe- 4 High
Column Address Strobe
Read/Write Input
Vcc
I/O0
I/O1
WE
RAS0
RAS1
Vss
I/O3
I/O2
NC
NC
NC
1
2
3
4
5
6
32
31
30
29
28
27
WE
A0 - A11
OE
Address Inputs
Output Enable
RAS2
NC
RAS3
A11
A10
A0
CAS
OE
NC
A9
A8
A7
7
8
26
25
24
23
22
21
20
19
I/O0 - I/O3
VCC
Data Input/Output
Power (+3.3V or +5.0V)
Ground
9
VSS
10
11
12
13
14
A1
A2
A6
A5
15
16
A3
Vcc
18
17
A4
Vss
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4727
GA14-4248-01
Revised 11/96
Page 1 of 24
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