IBMMicroelectronics
1394 Host Link Layer Controller
Enables IEEE 1394 standard PCI performance
Product Overview
tional channels for isochronous receive/
transmit.
Highlights
The IBM 21S650PFAis a high perfor-
mance IEEE1394 Link Layer Controller
with a PCIsystem interface.It is capable
of operating as a PCI master or slave and
supports long burst PCI transactions at
up to 33MHz.Its physical layer interface
supports data rates of100 Mbit/s,200
Mbit/s and 400 Mbit/s.Furthermore,a
DMA engine is incorporated to minimize
CPU intervention during packet transmis-
sion and reception.
• FullyIEEE1394-1995compatible
AsynchronousTransmission
The IBM 21S650PFAcan transmit and
receive all of the defined1394 packet
formats.Packets to be transmitted are read
from host memory and received packets
are written to host memory using DMA.To
avoiddeadlockconditions,twoDMA
contexts are used; one for request packets
andoneforresponsepackets. In addition,
the link supports automatic retry of packet
transmission following the reception of a
‘busyacknowledge.’
• Four bidirectional (transmit/receive)
isochronous DMA contexts
• Supports up to 63 isochronous channels
in transmit operation
• Uses Descriptor Based DMA(DB-DMA)
context structure
In addition,an interface to an external
configurationROMisprovided,allowing
system designers to store 1394 and PCI
configurationinformation.TheIBM
21S650PFAalsohasfeaturestosupportthe
transactionandbusmanagementlayers.
Figure1describesatypicalsystemthat
usestheIBM1394LinkController.ThePHY
chiphandlesthephysical layer protocol
and interface to the1394 serial bus cables.
• Two asynchronous DMA contexts for
transmit
• One asynchronous DMAcontext for
inbound packets
All received packets,with the exception of
self-ID packets,are directed to the
General Receive context.In compliance
with the OHCI specification,self-ID
packets,which are received during the
self-identification phase of bus initializa-
tion,are automatically routed to a single
designated host memory buffer.Each
time bus initialization occurs,the new self-
• Self-ID packets automatically routed to a
single designated host memory buffer
• Programmable1K byte transmit FIFO and
1K byte receive FIFO
DMAEngine
• Data rates: S100,S200,S400 Mb/s
The IBM 21S650PFA incorporates a DMA
engine to fetch packets from the system
memory and transmit them to the1394
bus,and to write received packets to the
system memory.The industry standard
Descriptor Based DMA(DB-DMA)
structure is used.Each asynchronousand
isochronous context is comprised of a
buffer descriptor list called a DMAcontext
program,stored in main memory.Buffers
are specified within the DMAcontext
program by DMA descriptors.
• Supports‘Isolation Barrier’and IBM’s
‘DynamicTermination’modes on the
PHY/Link interface
CPU
Host
DRAM
Bridge
PCI Bus
PCI
• Cycle Master capable
1394 Link
Component
Layer
• External configuration ROM interface
Controller
• PCI2.1interface
PHY
– Supports cache line commands
(memory write & invalidate,memory
read line, memory read multiple)
– Supports long burst PCI transactions
– No wait states
1394 Bus
1394 Bus
1394
Device
1394
Device
1394
Device
1394
Device
IBM's Link supports seven DMA contexts;
two for asynchronous transmit,one for
asynchronousreceive and four bidirec-
Figure 1
IBM [ IBM ]
