E S I
E S I
ADVANCED INFORMATION
Excel Semiconductor inc.
If the falling edge does not coincide with Serial Clock
(SCK) being Low, the Hold condition starts after
Serial Clock (SCK) next goes Low. Similarly, If the
rising edge does not coincide with Serial Clock
(SCK) being Low, the Hold condition ends after
Serial Clock (SCK) next goes Low (Figure 3).
Protection Modes
The SPI memory device boasts the following data
protection mechanisms
1) All instructions that modify data must be preceded
by a Write Enable(WREN) instruction to set the
Write Enable Latch (WEL) bit. This bit is returned to
its reset state by the following events :
- Power-up
During the Hold condition, the Serial Data Output
(SO) is high impedance, and Serial Data Input (SI)
and Serial Clock (SCK) are Don’t Care.
- WRDI instruction completion
Normally, the device remains selected, with Chip
Select (CS#) driven Low, for the entire duration of
the Hold condition. This ensures that the state of the
internal logic remains unchanged from the moment
of entering the Hold condition.
- WRSR instruction completion
- PP instruction completion
- SE instruction completion
- BE instruction completion
2) The Block Protect (BP2, BP1, BP0) bits allow part
of the memory to be configured as read-only. This is
the Software Protected Mode (SPM).
If Chip Select (CS#) goes High while the device is in
the Hold condition, this has the effect of resetting the
internal logic of the device. To restart communication
with the device, it is necessary to drive Hold
(HOLD#) High, and then to drive Chip Select (CS#)
Low. This prevents the device from going back to the
Hold condition.
3) The Write Protect (W#) signal works in coopera-
tion with the Status Register Write Disable (SRWD)
bit to enable write-protection. This is the Hardware
Protected Mode (HPM).
4) Program, Erase and Write Status Register instruc-
tions are checked to verify that they consist of a
number of clock pulses that is a multiple of eight,
before they are accepted for execution.
Table 1. Protected Area Sizes
Protected Memory
Area (Top Level)
Status Register Content
Memory Content
BP2 Bit BP1 Bit BP0 Bit
Protected Area
none
Unprotected Area
00000 ~ FFFFF
00000 ~ EFFFF
00000 ~ DFFFF
00000 ~ BFFFF
00000 ~ 7FFFF
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1 / 16
1 / 8
1 / 4
1 / 2
F0000 ~ FFFFF
E0000 ~ FFFFF
C0000 ~ FFFFF
80000 ~ FFFFF
00000 ~ FFFFF
+ parameter page
All
All
All
1
1
1
0
1
1
1
0
1
none
none
none
00000 ~ FFFFF
+ parameter page
00000 ~ FFFFF
+ parameter page
7
Rev. 0D May, 11, 2006
ES25P80
EXCELSEMI [ EXCEL SEMICONDUCTOR INC. ]
