E S I
E S I
ADVANCED INFORMATION
Excel Semiconductor inc.
SO
SPI Interface with
(CPOL, CPHA) =
(0,0) or (1,1)
SI
SCK
SCK SO
SI
SCK SO
SCK SO
SI
SI
Bus Master
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS1
CS2 CS3
W# HOLD#
W#
W#
HOLD#
CS#
HOLD#
CS#
CS#
Figure 1. Bus Master and Memory Devices on the SPI Bus
Note : The Write Protect (W#) and Hold (HOLD#) signals should be driven, High or Low as appropriate
CS#
CPOL CPHA
0
0
SCK
SCK
1
1
SI
MSB
SO
MSB
Figure 2. SPI Modes Supported
5
Rev. 0D May 11 , 2006
ES25P40