MP8798
Analog Input Multiplexer
Digital Interfaces
The MP8798 includes a 4-channel analog input multiplexer.
The relationship between the clock, the multiplexer address, the
WR and the output data is shown in Figure 10.
The logic encodes the outputs of the comparators into a bi-
nary code and latches the data in a D-type flip-flop for output.
Clock
The functional equivalent of the MP8798 (Figure 12.) is com-
posed of:
Sample N
Sample M
New Address
Sample
M+1
Old Address
t
t
t
CLKH2
CLKS2
WR
WR
1) Delay stage (tAP) from the clock to the sampling phase
t
AS
t
(φS).
AH
2) An ideal analog switch which samples VIN.
3) An ideal A/D which tracks and converts VIN with no
delay.
Address
4) A series of two DFF’s with specified hold (tHLD) and
delay (tDL) times.
N-1 Valid
Old Address
N Valid
Old Address
M Valid
New Address
DB0-DB9
N-2 Valid
t
= t
= 0
CLKS2
CLKH2
tAP, tHLD and tDL are specified in the Electrical Characteristics
table.
Figure 10. MUX Address Timing
t
AS
t
AH
φ S
A1, A0
WR
V
IN
A/D
D Q
D Q
DB9-DB0
CLK
t
WR
t
MUXEN1
t
AP
MP8798
MUXEN
(Internal Signal)
CLK
N
N+1
N-1
Figure 11. Analog MUX Timing
V
IN
t
HLD
t
DL
Reference Voltages
DB9-DB0
N
The input/output relationship is a function of VREF
IN = VIN – VREF(–)
VREF = VREF(+) – VREF(–)
DATA = 1023 (AIN/VREF
A system can increase total gain by reducing VREF
:
A
Figure 12. MP8798 Functional Equivalent
Circuit and Interface Timing
)
.
Rev. 3.00
9
EXAR [ EXAR CORPORATION ]
