MP7680
INPUT LA TCHES
DAC LA TCHES
LA11 - LA0
DA11 - DA0
12
8
R
I
8
FBA
DB11-DB4
(MSB)
D
E
Q
Q
OUT1A
B1
D
E
Q
Q
Q
Q
DAC
Latch
I
0
OUT2A
DB11-
DB8
4
8
D
E
MUX
B2
Latch
4
V
REFA
DB3-DB0
(LSB)
1
DB11 - DB0
12
R
I
8
FBB
D
E
Q
Q
OUT1B
B1
Latch
D
E
DAC
I
OUT2B
4
8
D
E
B2
Latch
4
V
REFB
DC11 - DC0
12
R
FBC
8
D
E
I
OUT1C
Q
Q
B1
Latch
D
E
DAC
I
OUT2C
4
8
D
E
B2
Latch
4
V
REFC
DD11 - DD0
12
R
I
8
FBD
D
E
Q
Q
OUT1D
B1
Latch
D
E
Disable-B1
DAC
B1/B2
I
OUT2D
4
D
E
B2
Latch
V
REFD
4
Enable A
Enable B
Enable C
Enable D
A1 (MSB)
A0 (LSB)
Latch
Address
Decoder
Transfer
CS
WR1
XFER WR2
Figure 3. Latches Control Logic
THEOR Y OF OPERA TION
Digital Interface
W riting to Input Latches
Figure 3. shows the internal control logic. The logic that
controls the writing of the input latches and the one that
controls the DAC latches are completely separated. It is
easy to understand how the MP7680/80A works by
understanding each basic operation.
By keeping B1/B2 = high, a 12-bit bus has direct access to
the 12 bits of the input latches. The condition CS = WR1 =
0 loads the values contained in the data bus DB11-DB0
into the input latch addresses by A1, A0 (Figure 4. ,
Table 1. ).
Rev. 3.10
8
EXAR [ EXAR CORPORATION ]
