MP7628
TIMING DIAGRAM READ CYCLE
A/B
R/W
t
S
t
t
NR
DSR
DS1
DS2
H
t
D
t
D
BUS (DN
)
3-state
Data (A)
3-state
Data (B)
Set up time for BUS, A/B, R/W
Minimum DS = low pulse
Minimum time between DS = low pulses
Data delay time
= 40 ns
t
t
t
t
S
= 320 ns
= 120 ns
= 200 ns
(min)
DSR
NR
D
t
R
= t + t
DSR NR
TIMING DIAGRAM WRITE CYCLE
DATA (D
)
Data (A)
A Select
Data (B)
B Select
N
A/B
t
DHLD
R/W
DS1
t
S
t
t
DSW
NW
H
L
H
DS2
tD
DAC A OUT
DAC B OUT
Last Data
Data (A)
t
S
+ t
D
Last Data
Data (B)
Set up time for BUS, A/B, R/W
Minimum DS = low pulse
Minimum time between DS = low pulses
Data delay time
= 40 ns
t
t
t
t
S
= 200 ns
= 120 ns
= 110 ns
(min)
DSW
NW
D
t
W
= t
+ t
DSW NW
MODE SELECTION TABLE
L = LOW STATE
H = HIGH STATE
X = DON’T CARE
DS1
DS2
A/B
R/W
MODE
DAC
L
L
H
H
L
H
H
L
H
L
H
L
H
L
H
L
H
L
X
H
L
L
L
L
L
H
H
H
H
L
WRITE
WRITE
WRITE
WRITE
READ
READ
READ
READ
WRITE
WRITE
HOLD
HOLD
HOLD
A
B
C
D
A
B
C
D
L
H
H
L
L
L
L
H
L
L
H
H
L
L
H
L
A & C
B & D
A/B/C/D
A/B/C/D
A/B/C/D
L
X
H
H
L
L
Rev. 2.00
6