MP7528
MICROPROCESSOR INTERFACE
Address Bus
A0-A15
Address Bus
A8-A15
A*
A*
DACA/DACB
Address
Decode
Logic
DACA/DACB
V
MA
Address
Decode
Logic
CS
DAC A
CPU
8085
DAC A
CS
CPU
6800
A+1**
MP7528
A+1**
φ2
WR
MP7528
WR
WR
DAC B
DB0
DB7
DAC B
ALE
DB0
Latch
8212
DB7
Data Bus
D0–D7
ADDR/Data Bus
AD0–AD7
Analog circuitry has been omitted for clarity
*A = Decoded 7528 DAC A Address
**A + 1 = Decoded 7528 DAC B Address
Analog circuitry has been omitted for clarity
*A = Decoded 7528 DAC A Address
**A + 1 = Decoded 7528 DAC B Address
NOTE:
8085 instruction SHLD (store H & L direct) can update
both DACS with data from H and L registers
Figure 2. MP7528 Dual DAC to 6800
CPU Interface
Figure 3. MP7528 Dual DAC to 8085
CPU Interface
PERFORMANCE CHARACTERISTICS
Graph 1. Relative Accuracy vs. Digital Code
5 V
Graph 2. Relative Accuracy vs. Digital Code
15 V
Rev. 2.00
9
EXAR [ EXAR CORPORATION ]
