MP1230A/31A/32A
THEORY OF OPERATION
V
DD
V
REF
DB11 (MSB) (DB3)
DB10 (DB2)
DB9 (DB1)
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
MSB
8-Bit
Input
Latch
DB8 (DB0)
R
I
FB
DB7
DB6
DB5
DB4
12-Bit
Multiplying
D/A
12-Bit
DAC
LE
OUT1
Converter
Register
4-Bit
Input
Latch
D
D
D
D
Q
Q
Q
Q
D
Q
Q
Q
Q
I
D
D
D
OUT2
LSB
LE
LE
BYTE1/BYTE2
CS
WR1
XFER
WR2
DGND
AGND
When LE = 1, Q Outputs Follow D Inputs
When LE = 0, Q Outputs are Latched
Figure 1. Functional Diagram
Transferring Data to the DAC Latches
Digital Interface
Figure 1. shows the internal control logic that controls the
writing of the input latches. It is easy to understand how the
MP1230A/31A/32A works by understanding each basic opera-
tion.
Onceoneoralltheinputlatcheshavebeenloaded, thecondi-
tion XFER= WR2= low transfers the content of the input latches
in the DAC latch. The outputs of the DAC latch change and the
DAC current (IOUT) will reach a new stable value within the set-
tling time tS (Figure 3.).
Writing to Input Latches
The condition BYTE1/BYTE2= high, CS = WR1 = 0 loads the
data bus DB11-DB4 into both input latches.
A second cycle with BYTE1/BYTE2 = low (Figure 2.) loads
the pins DB11-DB8 (DB3-DB0) into the 4-bit input latch.
Timing diagrams show the inputs CS and DB11-DB0 to be
stable during the entire writing cycle. In reality all the above sig-
nals can change (Figure 2.) as long as they meet the timing con-
ditions specified in the Electrical Characteristic Table.
XFER
WR2
or
or
DB11-0
CS
I
OUT
tS
BYTE1/BYTE2
DATA
Figure 3. Transfer Cycles from
Input Latches to DAC Latches
WR1
Figure 2. Write Cycles to Input Latches
Rev. 2.00
6
EXAR [ EXAR CORPORATION ]
