EUP7996
Block Diagram
Pin Functions
AVIN and PVIN
VREF
VREF provides the buffered output of the internal
reference voltage VDDQ/2. This output should be used
to provide the reference voltage for the Northbridge
chipset and memory. Since these inputs are typically
extremely high impedance, there should be little current
drawn from VREF. For improved performance, an output
bypass capacitor can be used, located close to the pin, to
help with noise. A ceramic capacitor in the range of
0.01uF to 0.1uF is recommended. This output remains
active during the shutdown state and thermal shutdown
events.
AVIN and PVIN are the input supply pins for the
EUP7996. AVIN is used to supply the internal control
circuitry. PVIN, however, is used exclusively to provide
the rail voltage for the output stage used to create VTT.
For SSTL-2 application, a good compromise would be to
connect the AVIN and PVIN directly together at 2.5V.
This eliminates the need for bypassing the two supply
pins separately. For SSTL-18 applications, it is
recommended to connect PVIN to 1.8V rail used for the
memory core and AVIN to a rail typically 2.5V supply.
The only limitation on input voltage selection is that
PVIN must be equal to or lower than AVIN.
VTT
VTT is a regulated output that is used to terminate the bus
resistors. It is capable of sinking and sourcing current
while regulating the output precisely to VDDQ/2. The
EUP7996 is capable of sinking and sourcing 1.5A
continues current. If a transient above the maximum
continues current is expected for a significant amount of
time then the output capacitor should be sized large
enough to prevent an excessive voltage drop. If large
current are required for longer duration, then care should
be taken to ensure that the maximum junction
temperature is not exceeded. If the junction temperature
exceeds the thermal shutdown point than VTT will
tri-state until the part returns below the hysteretic
trip-point.
VDDQ
VDDQ is the input used to create the internal reference
voltage for regulating VTT. The reference voltage is
generated from a resistor divider of two internal 50KΩ
resistors. This guarantees that VTT will track VDDQ/2
precisely. For SSTL-2 applications, VDDQ should be a
2.5V. The optimal implementation of VDDQ is as
remote sense. This can be achieved by connecting
VDDQ directly to the 2.5V rail at DIMM instead of
AVIN and PVIN. This ensures that the reference voltage
tracks the DDR memory rails precisely without a large
voltage drop from the power lines. For SSTL-18
applications, VDDQ will be a 1.8V signal.
VSENSE
SD
The purpose of the sense pin is to provide improved
remote load regulation. In most motherboard application
the termination resistors will connect to VTT in a long
plane. The VSENSE pin can be used by connecting it to the
middle of the bus. This will provide a better distribution
across the entire termination bus. When remote sense is
used, it may necessary to put a 0.1uf ceramic capacitor
beside the VSENSE pin to eliminate the noise that coupled
to VSENSE due to the long trace. VSENSE pin must be
connected to VTT if remote load regulation is not used.
SD can be used to put the regulator into low-power
mode. When SD is pulled low, the VTT power amplifier
is turned off and the VTT output is tri-state, but, VREF will
remain active, allowing those circuits requiring a
reference during the standby state to remain active.
DS7996 Ver2.5 June.2005
8
EUTECH [ EUTECH MICROELECTRONICS INC ]
