EUP3484S
Compensation Components
The input capacitor can be electrolytic, tantalum or
ceramic. When using electrolytic or tantalum capacitors,
a small, high quality ceramic capacitor, i.e. 0.1µF,
should be placed as close to the IC as possible. When
using ceramic capacitors, make sure that they have
enough capacitance to provide sufficient charge to
prevent excessive voltage ripple at input. The input
voltage ripple for low ESR capacitors can be estimated
by:
EUP3484S employs current mode control for easy
compensation and fast transient response. The system
stability and transient response are controlled through
the COMP pin. COMP is the output of the internal
transconductance error amplifier. A series capacitor-
resistor combination sets a pole-zero combination to
govern the characteristics of the control system.
The DC gain of the voltage feedback loop is given by:
I
V
V
OUT
V
LOAD
OUT
FB
ꢁ
V
=
1−
A
= R
G
A
IN
VDC
LOAD
CS
C1 f
V
V
V
IN
EA
IN
V
S
OUT
Where C1 is the input capacitance value.
Where VFB is the feedback voltage (0.925V), AVEA is
the error amplifier voltage gain, GCS is the current
sense transconductance and RLOAD is the load resistor
value.
For simplification, choose the input capacitor whose
RMS current rating greater than half of the maximum
load current.
Output Capacitor
The system has two poles of importance. One is due to
the compensation capacitor (C3) and the output resistor
of the error amplifier, and the other is due to the output
capacitor and the load resistor. These poles are located
at:
The output capacitor (C2) is required to maintain the
DC output voltage. Ceramic, tantalum, or low ESR
electrolytic capacitors are recommended. Low ESR
capacitors are preferred to keep the output voltage
ripple low. The output voltage ripple can be estimated
by:
G
EA
f
=
P1
P2
2π C3 A
V
f
V
VEA
OUT
L
OUT
ꢁV
OUT
=
1−
1
V
f
=
IN
S
2π C2 R
LOAD
1
R
+
ESR
8 f
C2
Where GEA is the error amplifier transconductance.
S
The system has one zero of importance, due to the
compensation capacitor (C3) and the compensation
resistor (R3). This zero is located at:
Where C2 is the output capacitance value and RESR is
the equivalent series resistance (ESR) value of the
output capacitor.
When using ceramic capacitors, the impedance at the
switching frequency is dominated by the capacitance
which is the main cause for the output voltage ripple.
For simplification, the output voltage ripple can be
estimated by:
1
f
=
Z1
2
π C3 R3
The system may have another zero of importance, if
the output capacitor has a large capacitance and/or a
high ESR value. The zero, due to the ESR and
capacitance of the output capacitor, is located at:
V
V
OUT
OUT
∆V
OUT
=
1 −
2
V
8 f
L C2
1
IN
S
f
=
ESR
2π C2 R
ESR
When using tantalum or electrolytic capacitors, the
ESR dominates the impedance at the switching
frequency. For simplification, the output ripple can be
approximated to:
In this case, a third pole set by the compensation
capacitor (C4) and the compensation resistor (R3) is
used to compensate the effect of the ESR zero on the
loop gain. This pole is located at:
V
V
OUT
OUT
∆V
OUT
=
1−
R
1
ESR
f
L
V
f
=
IN
S
P3
2π C4 R3
The characteristics of the output capacitor also affect
the stability of the regulation system. The EUP3484S
can be optimized for a wide range of capacitance and
ESR values.
The goal of compensation design is to shape the
converter transfer function to get a desired loop gain.
The system crossover frequency where the feedback
DS3484S Ver1.2 May 2012
9
EUTECH [ EUTECH MICROELECTRONICS INC ]
