EM6AA160TS
EtronTech
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The extended mode register is written by asserting low onCS ,RAS ,CAS , and WE .
The state of A0 ~ A12, BA0 and BA1 is written in the mode register in the same cycle asCS ,RAS ,CAS , and
WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into
the extended mode register. A1 is used for setting driver strength to normal, or weak. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for
specific codes.
Table 10. Extended Mode Resistor Bitmap
BA1
0
BA0
1
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RFU must be set to “0”
DS0
DLL
BA0 Mode
A1
0
Drive Strength
Normal
A0
0
DLL
Enable
0
1
MRS
EMRS
1
weak
1
Disable
Etron Confidential
9
Rev. 0.7
July 2008
ETRON [ ETRON TECHNOLOGY, INC. ]
