EtronTech
EM68C16CWQE
Ball Descriptions
Table 3. Ball Descriptions
Symbol
Type
Description
CK, CK#
Input
Differential Clock: CK, CK# are driven by the system clock. All SDRAM input signals are
sampled on the crossing of positive edge of CK and negative edge of CK#. Output (Read)
data is referenced to the crossings of CK and CK# (both directions of crossing).
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
LOW synchronously with clock, the internal clock is suspended from the next clock cycle
and the state of output and burst address is frozen as long as the CKE remains LOW.
When all banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes.
BA0-BA2
A0-A12
CS#
Input
Input
Input
Bank Address: BA0-BA2 define to which bank the BankActivate, Read, Write, or Bank
Precharge command is being applied.
Address Inputs: A0-A12 are sampled during the BankActivate command (row address A0-
A12) and Read/Write command (column address A0-A9 with A10 defining Auto Precharge).
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
RAS#
Input
Row Address Strobe: The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the crossing of positive edges of CK and
negative edge of CK#. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH" either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH" the BankActivate command is selected and
the bank designated by BA is turned on to the active state. When the WE# is asserted
"LOW" the Precharge command is selected and the bank designated by BA is switched to
the idle state after the precharge operation.
CAS#
WE#
Input
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the crossing of positive edges
of CK and negative edge of CK#. When RAS# is held "HIGH" and CS# is asserted "LOW"
the column access is started by asserting CAS# "LOW". Then, the Read or Write command
is selected by asserting WE# “HIGH" or “LOW".
Write Enable: The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the crossing of positive edges of CK and negative
edge of CK#. The WE# input is used to select the BankActivate or Precharge command
and Read or Write command.
LDQS,
LDQS#
UDQS
Input /
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe is
edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS
is for DQ0~7, UDQS is for DQ8~15. The data strobes LDOS and UDQS may be used in
single ended mode or paired with LDQS# and UDQS# to provide differential pair signaling
to the system during both reads and writes.A control bit at EMR (1)[A10] enables or disables
all complementary data strobe signals.
UDQS#
LDM,
UDM
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle.
LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
DQ0 - DQ15 Input /
Output
Data I/O: The Data bus input and output data are synchronized with positive and negative
edges of DQS/DQS#. The I/Os are byte-maskable during Writes.
ODT
Input
On Die Termination: ODT enables internal termination resistance. It is applied to each DQ,
LDQS/LDQS#, UDQS/UDQS#, LDM, and UDM signal. The ODT pin is ignored if the EMR
(1) is programmed to disable ODT.
VDD
VSS
Supply
Supply
Power Supply: +1.8V 0.1V
Ground
Rev. 1.6
5
May /2016
ETRON [ ETRON TECHNOLOGY, INC. ]
