欢迎访问ic37.com |
会员登录 免费注册
发布采购

EM639325TS-7IG 参数 Datasheet PDF下载

EM639325TS-7IG图片预览
型号: EM639325TS-7IG
PDF下载: 下载PDF文件 查看货源
内容描述: [4M x 32 bit Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器
文件页数/大小: 47 页 / 409 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
 浏览型号EM639325TS-7IG的Datasheet PDF文件第3页浏览型号EM639325TS-7IG的Datasheet PDF文件第4页浏览型号EM639325TS-7IG的Datasheet PDF文件第5页浏览型号EM639325TS-7IG的Datasheet PDF文件第6页浏览型号EM639325TS-7IG的Datasheet PDF文件第8页浏览型号EM639325TS-7IG的Datasheet PDF文件第9页浏览型号EM639325TS-7IG的Datasheet PDF文件第10页浏览型号EM639325TS-7IG的Datasheet PDF文件第11页  
EM639325  
EtronTech  
Operation Mode  
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.  
Table 4 shows the truth table for the operation commands.  
Table 4. Truth Table (Note (1), (2))  
Command  
State CKEn-1 CKEn DQM(6) BA0,1 A10 A11, A9-0 CS# RAS# CAS# WE#  
Idle(3)  
H
H
H
H
H
X
X
X
X
X
X
X
X
V
V
V
V
X
V
V
Row address  
L
L
L
L
L
L
L
H
H
H
L
H
L
L
L
L
BankActivate  
BankPrecharge  
PrechargeAll  
Any  
L
H
L
X
X
Any  
L
Active(3)  
Active(3)  
H
H
Write  
Column  
address  
(A0 ~ A7)  
Write and AutoPrecharge  
H
L
Active(3)  
Active(3)  
H
H
X
X
V
V
V
V
L
L
L
H
H
L
L
H
H
Read  
Column  
address  
(A0 ~ A7)  
Read and Autoprecharge  
H
Mode Register Set  
No-Operation  
Idle  
Any  
H
H
H
H
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
OP code  
L
L
L
H
H
X
L
L
H
H
X
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Active(4)  
L
Burst Stop  
Device Deselect  
AutoRefresh  
Any  
H
L
X
H
H
X
H
X
V
X
H
X
X
H
X
X
Idle  
SelfRefresh Entry  
SelfRefresh Exit  
Idle  
L
L
L
Idle  
(SelfRefresh)  
H
H
L
X
H
X
V
X
H
X
X
H
X
X
X
H
X
V
X
H
X
X
H
X
X
Clock Suspend Mode Entry  
Power Down Mode Entry  
Active  
Any(5)  
Active  
H
H
L
L
X
X
X
X
X
X
X
X
H
L
H
L
Clock Suspend Mode Exit  
Power Down Mode Exit  
L
L
H
H
X
X
X
X
X
X
X
X
X
H
L
Any  
(PowerDown)  
Data Write/Output Enable  
Data Mask/Output Disable  
Active  
Active  
H
H
X
X
L
X
X
X
X
X
X
X
X
H
Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high  
2. CKEn signal is input level when commands are provided.  
CKEn-1 signal is input level one clock cycle before the commands are provided.  
3. These are states of bank designated by BA signal.  
4. Device state is 1, 2, 4, 8, and full page burst operation.  
5. Power Down Mode can not enter in the burst operation.  
When this command is asserted in the burst cycle, device state is clock suspend mode.  
6. DQM0-3  
Rev. 2.1  
7
Aug. /2015