EtronTech
EM638165
6
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
DIN
A
DIN A
DIN
A
DIN A
3
don't care
DQ0 - DQ3
0
1
2
The first data element and the write
Extra data is masked.
are registered on the same clock edge.
Burst Write Operation
(Burst Length = 4, CAS# Latency = 1, 2, 3)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
1 Clk Interval
DIN A
DIN B
0
DIN B
DIN B
DIN B
3
DQ's
0
1
2
Write Interrupted by a Write
(Burst Length = 4, CAS# Latency = 1, 2, 3)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0
T 1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
CAS# latency=2
NOP
WRITE A
READ B
don't care
don't care
NOP
NOP
NOP
DOUT B
DOUT B
DIN A
0
DOUT B
DOUT B
1
2
3
0
t
, DQ's
CK2
CAS# latency=3
, DQ's
DOUT B
DOUT B
DOUT B
DOUT B
DIN A
0
don't care
t
0
1
2
3
CK3
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the write is masked.
Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
Preliminary
Rev 0.6
Feb. 2001
9