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EM637327 参数 Datasheet PDF下载

EM637327图片预览
型号: EM637327
PDF下载: 下载PDF文件 查看货源
内容描述: 1Mega ×32 SGRAM [1Mega x 32 SGRAM]
分类和应用:
文件页数/大小: 78 页 / 1161 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM637327  
1Mega x 32 SGRAM  
Operation Mode  
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.  
Table 2 shows the truth table for the operation commands.  
Table 2. Truth Table (Note (1), (2) )  
Command  
State CKEn-1 CKEn DQM(7) BS A8 A  
CS# RAS# CAS# WE# DSF  
DDR  
Idle(3)  
Idle(3)  
Any  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
X
V
V
V
V
V
V
V
X
X
X
X
X
X
X
V
V
L
V
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
X
L
L
H
H
H
H
L
H
H
L
L
H
L
BankActivate & Masked Write Disable  
BankActivate & Masked Write Enable  
BankPrecharge  
V
X
L
PrechargeAll  
Any  
H
L
X
L
L
L
Active(3)  
Active(3)  
Active(3)  
Active(3)  
Active(3)  
Active(3)  
Idle  
V
H
H
H
H
H
H
L
L
L
Write  
Block Write Command  
Write and AutoPrecharge  
Block Write and AutoPrecharge  
Read  
L
V
L
L
H
L
H
H
L
V
L
L
V
L
L
H
L
V
L
H
H
L
Read and Autoprecharge  
Mode Register Set  
Special Mode Register Set  
No-Operation  
H
L
V
L
L
V
L
L
Idle(5)  
X
X
X
X
X
X
X
V
L
L
L
H
X
L
Any  
X
H
H
X
L
H
H
X
L
H
L
Active(4)  
Any  
X
Burst Stop  
Device Deselect  
X
X
H
H
X
H
X
X
H
X
X
H
X
X
X
L
AutoRefresh  
Idle  
X
SelfRefresh Entry  
SelfRefresh Exit  
Idle  
X
L
L
L
Idle  
H
X
X
H
X
X
H
X
X
H
X
X
X
H
X
X
H
X
X
H
X
X
X
X
X
X
L
(SelfRefresh)  
Clock Suspend Mode Entry  
Power Down Mode Entry  
Active  
Any(6)  
H
H
L
L
X
X
X
X
X
X
X
X
Clock Suspend Mode Exit  
Power Down Mode Exit  
Active  
L
L
H
H
X
X
X
X
X
X
X
X
X
X
L
Any  
(PowerDown)  
Data Write/Output Enable  
Data Mask/Output Disable  
Active  
Active  
H
H
X
X
L
X
X
X
X
X
X
X
X
H
Note:  
1. V=Valid X=Don't Care L=Low level H=High level  
2. CKEn signal is input level when commands are provided.  
CKEn-1 signal is input level one clock cycle before the commands are provided.  
3. These are states of bank designated by BS signal.  
4. Device state is 1, 2, 4, 8, and full page burst operation.  
5. The Special Mode Register Set is also available in Row Active State.  
6. Power Down Mode can not enter in the burst operation.  
When this command is asserted in the burst cycle, device state is clock suspend mode.  
7. DQM0-3  
Preliminary  
August 1999  
5