EtronTech
EM637327
1Mega x 32 SGRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
Bank,
Row
ADDRESS
Bank(s)
tRP
COMMAND
READ
A
NOP
NOP
NOP
NOP
NOP
Precharge
DOUT A
NOP
Activate
CAS# latency=1
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
, DQ's
CK1
CAS# latency=2
, DQ's
DOUT A
2
DOUT A
DOUT A
0
1
3
t
CK2
CAS# latency=3
, DQ's
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
CK3
Read to Precharge
(CAS# Latency = 1, 2, 3)
6
7
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A8 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in
this command and the auto precharge function is ignored.
Write command
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A8 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
DIN
A
DIN A
DIN
A
DIN A
3
don't care
DQ0 - DQ3
0
1
2
The first data element and the write
are registered on the same clock edge.
Extra data is masked.
Burst Write Operation
(Burst Length = 4, CAS# Latency = 1, 2, 3)
Any Write performed to a row that was opened via an BankActivate & Masked Write Enable
command is a masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected
column location subject to the data stored in the Mask register. The overall mask consists of the
DQM inputs, which mask on a per-byte basis, and the Mask register, which masks also on a per-bit
basis. This is shown in the following block diagram.
Preliminary
August 1999
9
ETRON [ ETRON TECHNOLOGY, INC. ]
